Working tests
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obj_dir/Vcpu.cpp: cpu.v test_main.cpp
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verilator -Wall -cc cpu.v --exe test_main.cpp
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obj_dir/Vcpu: obj_dir/Vcpu.cpp
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cd obj_dir; make -j -f Vcpu.mk Vcpu
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test: obj_dir/Vcpu
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obj_dir/Vcpu
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clean:
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rm -rf obj_dir
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3
README
3
README
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A WIP Chip8 Verilog CPU.
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A WIP Chip8 Verilog CPU.
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May, in the future, contain other components (VGA, SRAM, PS2 and SD card) in order to synthesize this as a console on a Spartan devboard or something.
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May, in the future, contain other components (VGA, SRAM, PS2 and SD card) in order to synthesize this as a console on a Spartan devboard or something.
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To run tests:
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make test
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