Basic CPU working, and some verilator testcases
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0e21c36caf
commit
9963c33ff6
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@ -0,0 +1 @@
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*.swp
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133
cpu.v
133
cpu.v
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@ -3,23 +3,27 @@
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`timescale 1ns / 1ps
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module core (
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/* verilator lint_off UNDRIVEN */
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/* verilator lint_off UNUSED */
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/* verilator lint_off LITENDIAN */
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module cpu (
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input reset,
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input cpu_clock,
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input timer_clock,
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input [15:0] keypad
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);
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// 4k (12 bits) of 8-bit ram
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reg [7:0] ram[0:4095];
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reg [7:0] ram[0:4095]/* verilator public */;
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// 16 8-bit V registers
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reg [7:0] v[0:15];
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reg [7:0] vr[0:15]/* verilator public */;
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// 16-bit I register
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reg [15:0] i;
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// 12-bit program counter
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reg [11:0] pc;
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// 8-bit stack pointer
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reg [7:0] sp;
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reg [11:0] pc/* verilator public */;
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// 16-element, 12-bit stack
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reg [11:0] stack [0:15];
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// 4-bit stack pointer
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reg [3:0] sp;
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// internal cycle counter (0 - fetch)
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`define FETCH 0
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@ -29,35 +33,55 @@ module core (
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// Instruction register
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reg [15:0] ins;
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wire family = (ins >> 12);
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wire [3:0] family = ins[15:12];
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// ALU operation
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wire [3:0] alu_op = ins & 4'hF;
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// ALU source registers
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wire [3:0] alu_x = (ins >> 8) & 4'hF;
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wire [3:0] alu_y = (ins >> 4) & 4'hF;
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// ALU immediate
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wire [7:0] kk = ins & 8'hFF;
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wire [11:0] nnn = ins & 12'hFFF;
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wire [3:0] alu_op = ins[3:0];
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wire is_alu_op = (c == `EXECUTE) && (family == 8);
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// Source register indexes
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wire [3:0] x = ins[11:8];
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wire [3:0] y = ins[7:4];
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// Immediates
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wire [7:0] kk = ins[7:0];
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wire [11:0] nnn = ins[11:0];
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// Jump register
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reg[15:0] jmp;
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reg[11:0] jmp;
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// Should jump on FETCH?
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reg should_jmp;
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always @(cpu_clock)
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always @(posedge cpu_clock)
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begin
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if (!reset) begin
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i <= 0;
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pc <= 0;
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sp <= 0;
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should_jmp <= 0;
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c <= 0;
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vr[0] <= 0;
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vr[1] <= 0;
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vr[2] <= 0;
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vr[3] <= 0;
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vr[4] <= 0;
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vr[5] <= 0;
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vr[6] <= 0;
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vr[7] <= 0;
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vr[8] <= 0;
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vr[9] <= 0;
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vr[10] <= 0;
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vr[11] <= 0;
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vr[12] <= 0;
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vr[13] <= 0;
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vr[14] <= 0;
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vr[15] <= 0;
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end else begin
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case(c)
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`FETCH: begin
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ins <= ram[pc] << 8 | ram[pc + 1];
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ins <= {ram[pc], ram[pc + 1]};
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c <= 1;
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end
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`EXECUTE: begin
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`EXECUTE: begin
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case (family)
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// Jump to address
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1: begin
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@ -67,87 +91,70 @@ module core (
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// Call address
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2: begin
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should_jmp <= 1;
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ram[sp] <= pc;
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stack[sp] <= pc;
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sp <= sp + 1;
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jmp <= nnn;
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end
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// Skip next if Vx == kk (3xkk)
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3: begin
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if (v[alu_x] == kk) begin
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if (vr[x] == kk) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Skip next if Vx != kk (4xkk)
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4: begin
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if (v[alu_x] != kk) begin
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if (vr[x] != kk) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Skip next if Vx == Vy (5xy0)
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5: begin
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if (v[alu_x] == v[alu_y]) begin
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if (vr[x] == vr[y]) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Vx <= kk
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6: v[alu_x] <= kk;
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6: vr[x] <= kk;
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// Vx += kk
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7: v[alu_x] <= v[alu_x] + kk;
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// ALU operation
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8: case(alu_op)
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0: v[alu_x] <= v[alu_y];
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1: v[alu_x] <= v[alu_x] | v[alu_y];
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2: v[alu_x] <= v[alu_x] & v[alu_y];
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3: v[alu_x] <= v[alu_x] ^ v[alu_y];
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4: { v[15], v[alu_x] } <= v[alu_x] + v[alu_y];
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5: { v[15], v[alu_x] } <= (v[alu_x] - v[alu_y]) ^ (1 << 8);
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6: begin
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v[15] <= v[alu_x][0];
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v[alu_x] <= v[alu_x] >> 1;
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end
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7: { v[15], v[alu_x] } <= (v[alu_y] - v[alu_x]) ^ (1 << 8);
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15: begin
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v[15] <= v[alu_x][7];
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v[alu_x] <= v[alu_x] << 1;
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end
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endcase
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7: vr[x] <= vr[x] + kk;
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// Skip if Vx != Vy (9xy0)
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9: begin
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if (v[alu_x] != v[alu_y]) begin
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if (vr[x] != vr[y]) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Set I to nnn
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10: i <= nnn;
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10: i <= {4'h0, nnn};
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// Jump to nnn + V0
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11: begin
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should_jmp <= 1;
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jmp <= nnn + v[0];
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jmp <= nnn + {4'h0, vr[0]};
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end
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// Set Vx to random and kk
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// TODO: undo fair dice roll
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12: v[alu_x] <= 42 & kk;
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12: vr[x] <= 42 & kk;
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// TODO: draw sprites
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13: begin end
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// Key functions
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14: begin
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if (kk == 8'h9E) begin
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if ((keypad >> alu_x) & 1) begin
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if (keypad[x]) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end else if (kk == 8'hA1) begin
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if (((keypad >> alu_x) & 1) == 0) begin
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if (~keypad[x]) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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end
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endcase
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c <= 2;
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end
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`WRITEBACK: begin
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if (should_jmp) begin
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@ -156,6 +163,34 @@ module core (
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pc <= pc + 2;
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end
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should_jmp <= 0;
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c <= 0;
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end
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endcase
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end
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end
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// ALU
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always @(posedge cpu_clock)
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begin
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if (is_alu_op) begin
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case(alu_op)
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0: vr[x] <= vr[y];
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1: vr[x] <= vr[x] | vr[y];
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2: vr[x] <= vr[x] & vr[y];
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3: vr[x] <= vr[x] ^ vr[y];
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4: { vr[15], vr[x] } <= {8'b0, vr[x]} + {8'b0, vr[y]};
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5: begin
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vr[x] <= vr[x] - vr[y];
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vr[15] <= {7'b0, vr[x] >= vr[y]};
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end
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6: begin
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vr[15] <= {7'b0, vr[x][0]};
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vr[x] <= vr[x] >> 1;
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end
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7: { vr[15], vr[x] } <= ({8'b0, vr[y]} - {8'b0, vr[x]}) ^ (1 << 8);
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15: begin
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vr[15] <= {7'b0, vr[x][7]};
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vr[x] <= vr[x] << 1;
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end
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endcase
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end
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@ -0,0 +1,102 @@
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#include "Vcpu.h"
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#include "Vcpu_cpu.h"
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#include "verilated.h"
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Vcpu *top;
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void dump_regs(void)
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{
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printf("-> regs:\n");
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for (int i = 0; i < 8; i++)
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printf(" %i: 0x%02x\n", i, top->v->vr[i]);
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}
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void step(void)
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{
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top->cpu_clock = 0;
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top->eval();
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top->cpu_clock = 1;
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top->eval();
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}
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void step3(void)
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{
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step(); step(); step();
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}
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void run_instruction(uint16_t instruction)
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{
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top->v->ram[0] = instruction >> 8;
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top->v->ram[1] = instruction & 0xFF;
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top->v->pc = 0;
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}
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void reset(void)
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{
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top->reset = 0;
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step3(); step3();
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top->reset = 1;
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}
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void test_alu_instruction(uint8_t x, uint8_t y, uint16_t ins, uint8_t expected)
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{
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printf("INS %04x: ", ins);
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reset();
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top->v->vr[1] = x;
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top->v->vr[2] = y;
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run_instruction(ins);
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step3();
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if (top->v->vr[1] != expected)
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printf(" FAIL! Expected %02x, got %02x.\n", expected, top->v->vr[1]);
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else
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printf(" OK.\n");
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}
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void test_alu_instruction_vf(uint8_t x, uint8_t y, uint16_t ins, uint8_t expected, uint8_t evf)
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{
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printf("INS %04x: ", ins);
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reset();
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top->v->vr[1] = x;
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top->v->vr[2] = y;
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run_instruction(ins);
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step3();
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if (top->v->vr[1] != expected)
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printf(" FAIL! Expected %02x, got %02x.\n", expected, top->v->vr[1]);
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else
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{
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if (top->v->vr[15] != evf)
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printf(" FAIL! Expected VF %02x, got %02x.\n", evf, top->v->vr[15]);
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else
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printf(" OK.\n");
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}
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}
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int main(int argc, char **argv)
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{
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Verilated::commandArgs(argc, argv);
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top = new Vcpu;
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// LD
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printf("LD ");
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test_alu_instruction(0x00, 0x45, 0x8120, 0x45);
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// OR
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printf("OR ");
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test_alu_instruction(0x0F, 0xF0, 0x8121, 0xFF);
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// AND
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printf("AND ");
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test_alu_instruction(0xF0, 0x45, 0x8122, 0x40);
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// XOR
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printf("XOR ");
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test_alu_instruction(0xFF, 0x11, 0x8123, 0xEE);
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// ADD
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printf("ADD (no carry) ");
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test_alu_instruction_vf(0x10, 0x25, 0x8124, 0x35, 0x00);
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printf("ADD (with carry) ");
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test_alu_instruction_vf(0xF0, 0x43, 0x8124, 0x33, 0x01);
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// SUB
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printf("SUB (no borrow) ");
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test_alu_instruction_vf(0x45, 0x15, 0x8125, 0x30, 0x01);
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printf("SUB (zero, no borrow) ");
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test_alu_instruction_vf(0x45, 0x45, 0x8125, 0x00, 0x01);
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printf("SUB (borrow) ");
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test_alu_instruction_vf(0x15, 0x45, 0x8125, 0xD0, 0x00);
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}
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