Working tests

2014-01-04 13:56:21 +01:00 · 2014-01-04 13:56:21 +01:00 · c1fd5a6c12
parent 9963c33ff6
commit c1fd5a6c12
2 changed files with 14 additions and 0 deletions
--- a/11
+++ b/11
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+obj_dir/Vcpu.cpp: cpu.v test_main.cpp
+	verilator -Wall -cc cpu.v --exe test_main.cpp
+
+obj_dir/Vcpu: obj_dir/Vcpu.cpp
+	cd obj_dir; make -j -f Vcpu.mk Vcpu
+
+test: obj_dir/Vcpu
+	obj_dir/Vcpu
+
+clean:
+	rm -rf obj_dir
--- a/3
+++ b/3
@ -1,3 +1,6 @@
 A WIP Chip8 Verilog CPU.

 May, in the future, contain other components (VGA, SRAM, PS2 and SD card) in order to synthesize this as a console on a Spartan devboard or something.
+
+To run tests:
+    make test