Make verilator like our source
Signed-off-by: Sergiusz 'q3k' Bazański <q3k@q3k.org>master
parent
4c6fbc8378
commit
7b562944ca
|
@ -22,6 +22,7 @@
|
||||||
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
|
||||||
|
/* verilator lint_off UNUSED */
|
||||||
module qm_decode(
|
module qm_decode(
|
||||||
/// datapath
|
/// datapath
|
||||||
// from Fetch
|
// from Fetch
|
||||||
|
@ -29,7 +30,7 @@ module qm_decode(
|
||||||
// backtraced from decode
|
// backtraced from decode
|
||||||
input wire [4:0] di_WA,
|
input wire [4:0] di_WA,
|
||||||
input wire di_WE,
|
input wire di_WE,
|
||||||
input wire [31:0] di_WD
|
input wire [31:0] di_WD,
|
||||||
|
|
||||||
output wire [31:0] do_RSVal,
|
output wire [31:0] do_RSVal,
|
||||||
output wire [31:0] do_RTVal,
|
output wire [31:0] do_RTVal,
|
||||||
|
|
|
@ -21,7 +21,7 @@
|
||||||
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
//
|
|
||||||
/* verilator lint_off UNUSED */
|
/* verilator lint_off UNUSED */
|
||||||
module qm_icache(
|
module qm_icache(
|
||||||
input wire [31:0] address,
|
input wire [31:0] address,
|
||||||
|
|
|
@ -39,7 +39,7 @@ module qm_regfile(
|
||||||
reg [31:0] rf [31:0];
|
reg [31:0] rf [31:0];
|
||||||
|
|
||||||
always @(wd3) begin
|
always @(wd3) begin
|
||||||
if (we3 && wa != 0) begin
|
if (we3 && wa3 != 0) begin
|
||||||
rf[wa3] = wd3;
|
rf[wa3] = wd3;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
|
@ -33,20 +33,19 @@ void test_decode(void)
|
||||||
Vqm_decode *decode = new Vqm_decode;
|
Vqm_decode *decode = new Vqm_decode;
|
||||||
|
|
||||||
// set r5 to 666 and r4 to 0xdeadbeef
|
// set r5 to 666 and r4 to 0xdeadbeef
|
||||||
decode->dbg_wa = 5;
|
decode->di_WA = 5;
|
||||||
decode->dbg_wd = 666;
|
decode->di_WD = 666;
|
||||||
decode->dbg_we = 1;
|
decode->di_WE = 1;
|
||||||
decode->eval();
|
decode->eval();
|
||||||
decode->dbg_wa = 4;
|
decode->di_WA = 4;
|
||||||
decode->dbg_wd = 0xdeadbeef;
|
decode->di_WD = 0xdeadbeef;
|
||||||
decode->eval();
|
decode->eval();
|
||||||
decode->dbg_we = 0;
|
decode->di_WE = 0;
|
||||||
|
|
||||||
decode->di_IR = 0x20a40539;
|
decode->di_IR = 0x20a40539;
|
||||||
decode->eval();
|
decode->eval();
|
||||||
|
|
||||||
std::cout << std::hex << decode->do_IR << std::endl;
|
std::cout << std::hex << decode->do_RSVal << std::endl;
|
||||||
std::cout << std::hex << decode->do_A << std::endl;
|
std::cout << std::hex << decode->do_RTVal << std::endl;
|
||||||
std::cout << std::hex << decode->do_B << std::endl;
|
|
||||||
std::cout << std::dec << decode->do_Imm << std::endl;
|
std::cout << std::dec << decode->do_Imm << std::endl;
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue