diff --git a/rtl/verilog/qm_decode.v b/rtl/verilog/qm_decode.v index 6dc77e8..9dd8b23 100644 --- a/rtl/verilog/qm_decode.v +++ b/rtl/verilog/qm_decode.v @@ -22,6 +22,7 @@ // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/* verilator lint_off UNUSED */ module qm_decode( /// datapath // from Fetch @@ -29,7 +30,7 @@ module qm_decode( // backtraced from decode input wire [4:0] di_WA, input wire di_WE, - input wire [31:0] di_WD + input wire [31:0] di_WD, output wire [31:0] do_RSVal, output wire [31:0] do_RTVal, diff --git a/rtl/verilog/qm_icache.v b/rtl/verilog/qm_icache.v index a6e63fb..8064948 100644 --- a/rtl/verilog/qm_icache.v +++ b/rtl/verilog/qm_icache.v @@ -21,7 +21,7 @@ // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// + /* verilator lint_off UNUSED */ module qm_icache( input wire [31:0] address, diff --git a/rtl/verilog/qm_regfile.v b/rtl/verilog/qm_regfile.v index 9b02894..4f484dc 100644 --- a/rtl/verilog/qm_regfile.v +++ b/rtl/verilog/qm_regfile.v @@ -39,7 +39,7 @@ module qm_regfile( reg [31:0] rf [31:0]; always @(wd3) begin - if (we3 && wa != 0) begin + if (we3 && wa3 != 0) begin rf[wa3] = wd3; end end diff --git a/test/test_decode.cpp b/test/test_decode.cpp index fea307a..e27b58a 100644 --- a/test/test_decode.cpp +++ b/test/test_decode.cpp @@ -33,20 +33,19 @@ void test_decode(void) Vqm_decode *decode = new Vqm_decode; // set r5 to 666 and r4 to 0xdeadbeef - decode->dbg_wa = 5; - decode->dbg_wd = 666; - decode->dbg_we = 1; + decode->di_WA = 5; + decode->di_WD = 666; + decode->di_WE = 1; decode->eval(); - decode->dbg_wa = 4; - decode->dbg_wd = 0xdeadbeef; + decode->di_WA = 4; + decode->di_WD = 0xdeadbeef; decode->eval(); - decode->dbg_we = 0; + decode->di_WE = 0; decode->di_IR = 0x20a40539; decode->eval(); - std::cout << std::hex << decode->do_IR << std::endl; - std::cout << std::hex << decode->do_A << std::endl; - std::cout << std::hex << decode->do_B << std::endl; + std::cout << std::hex << decode->do_RSVal << std::endl; + std::cout << std::hex << decode->do_RTVal << std::endl; std::cout << std::dec << decode->do_Imm << std::endl; }