188 lines
6.0 KiB
Verilog
188 lines
6.0 KiB
Verilog
// Copyright (c) 2014, Segiusz 'q3k' Bazanski <sergiusz@bazanski.pl>
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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/* verilator lint_off UNUSED */
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module qm_icache(
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input wire [31:0] address,
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input wire reset,
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input wire clk,
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// to the consumer (CPU fetch stage)
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output wire hit,
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output wire stall,
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output wire [31:0] data,
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input wire enable,
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// to the memory controller (no wishbone yet...)
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// the cache is currently only backed in 1GBit RAM via this controller
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// this RAM is mapped 0x80000000 - 0x90000000
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output wire mem_cmd_clk, // we will keep this synchronous to the input clock
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output wire mem_cmd_en,
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output wire [2:0] mem_cmd_instr,
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output wire [5:0] mem_cmd_bl,
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output wire [29:0] mem_cmd_addr,
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input wire mem_cmd_full,
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input wire mem_cmd_empty,
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output wire mem_rd_clk,
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output wire mem_rd_en,
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input wire [6:0] mem_rd_count,
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input wire mem_rd_full,
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input wire [31:0] mem_rd_data,
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input wire mem_rd_empty
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);
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// 4k cache lines -> 16kword cache
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reg [144:0] lines [4095:0];
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/// internal signals
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// the bit used to mark valid lines (flips when we flush the cache)
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reg valid_bit;
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wire [11:0] index;
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wire index_valid;
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wire [15:0] index_tag;
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wire [15:0] address_tag;
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wire [1:0] address_word;
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assign index = address[15:4];
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assign index_valid = lines[index][144];
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assign index_tag = lines[index][143:128];
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assign address_tag = address[31:16];
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assign address_word = address[3:2];
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assign mem_rd_clk = clk;
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assign mem_cmd_clk = clk;
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// reset condition
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generate
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genvar i;
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for (i = 0; i < 4096; i = i + 1) begin: ruchanie
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always @(posedge clk) begin
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if (reset) begin
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lines[0] <= {145'b0};
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end
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end
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end
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endgenerate
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always @(posedge clk) begin
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if (reset) begin
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valid_bit <= 1;
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memory_read_state <= 0;
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mem_cmd_en <= 0;
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mem_cmd_bl <= 0;
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mem_cmd_instr <= 0;
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mem_cmd_addr <= 0;
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mem_rd_en <= 0;
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end
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end
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// read condition
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always @(*) begin
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if (enable) begin
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// is this in the RAM region?
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if (32'h80000000 <= address && address < 32'h90000000) begin
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// do we have a hit?
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if (index_valid == valid_bit && index_tag == address_tag) begin
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if (address_word == 2'b00)
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data = lines[index][31:0];
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else if (address_word == 2'b01)
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data = lines[index][63:32];
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else if (address_word == 2'b10)
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data = lines[index][95:64];
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else
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data = lines[index][127:96];
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hit = 1;
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stall = 0;
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end else begin
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hit = 0;
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stall = 1;
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end
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end else begin
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hit = 1;
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stall = 0;
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data = 32'h00000000;
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end
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end else begin
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hit = 0;
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stall = 0;
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end
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end
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// if we are stalling, it means that our consumer is waiting for us to
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// read memory and provide it data
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reg [2:0] memory_read_state;
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always @(posedge clk) begin
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if (stall && !reset && enable) begin
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case (memory_read_state)
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0: begin // assert command
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mem_cmd_instr <= 1; // read
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mem_cmd_bl <= 3; // four words
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mem_cmd_addr <= {1'b0, address[28:0]};
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mem_cmd_en <= 0;
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memory_read_state <= 1;
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end
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1: begin // assert enable
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mem_cmd_en <= 1;
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memory_read_state <= 2;
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mem_rd_en <= 1;
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end
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2: begin // wait for first word
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mem_cmd_en <= 0;
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if (!mem_rd_empty) begin
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lines[index][31:0] <= mem_rd_data;
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memory_read_state <= 3;
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end
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end
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3: begin // wait for second word
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if (!mem_rd_empty) begin
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lines[index][63:32] <= mem_rd_data;
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memory_read_state <= 4;
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end
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end
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4: begin // wait for third word
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if (!mem_rd_empty) begin
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lines[index][95:64] <= mem_rd_data;
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memory_read_state <= 5;
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end
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end
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5: begin // wait for fourth word
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if (!mem_rd_empty) begin
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lines[index][127:96] <= mem_rd_data;
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memory_read_state <= 0;
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mem_rd_en <= 0;
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// write tag
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lines[index][143:128] <= address_tag;
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// and valid bit - our cominatorial logic will now turn
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// off stalling and indicate a hit to the consumer
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lines[index][144] <= valid_bit;
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end
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end
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endcase
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end
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end
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endmodule
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