initial commit
twl
commit
1b595ed568
|
|
@ -0,0 +1,165 @@
|
|||
GNU LESSER GENERAL PUBLIC LICENSE
|
||||
Version 3, 29 June 2007
|
||||
|
||||
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
|
||||
This version of the GNU Lesser General Public License incorporates
|
||||
the terms and conditions of version 3 of the GNU General Public
|
||||
License, supplemented by the additional permissions listed below.
|
||||
|
||||
0. Additional Definitions.
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||||
|
||||
As used herein, "this License" refers to version 3 of the GNU Lesser
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General Public License, and the "GNU GPL" refers to version 3 of the GNU
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"The Library" refers to a covered work governed by this License,
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A "Combined Work" is a work produced by combining or linking an
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The "Minimal Corresponding Source" for a Combined Work means the
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6. Revised Versions of the GNU Lesser General Public License.
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|
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|
|
@ -0,0 +1,14 @@
|
|||
DSI Core Readme
|
||||
------------------------
|
||||
|
||||
0. Disclaimer
|
||||
|
||||
This project implements a MIPI DSI (MIPI Display Serial Interface) Verilog core.
|
||||
Since the DSI specification is non-public and requires an NDA, the core is based on
|
||||
using bits and pieces available throughout the Web: presentations, display controller/SOC
|
||||
datasheets, various application notes and Android kernel drivers. The author is not
|
||||
associated in any way with the MIPI Alliance. The core is provided as-is, it has never been
|
||||
verified for compliance with the DSI standard and it probably lacks many of its features.
|
||||
To sum up: you use it at your own risk, there's no warranty.
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
*.zip
|
||||
work
|
||||
transcript
|
||||
*.vlf
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
files = ["dphy_lane.v",
|
||||
"dphy_serdes.v",
|
||||
"dsi_core.v",
|
||||
"dsi_fifo.v",
|
||||
"dsi_packer.v",
|
||||
"dsi_packet_assembler.v",
|
||||
"dsi_test_image_gen.v",
|
||||
"dsi_timing_gen.v",
|
||||
"dsi_utils.v"]
|
||||
|
|
@ -0,0 +1,275 @@
|
|||
/*
|
||||
* DSI Core
|
||||
* Copyright (C) 2013 twl <twlostow@printf.cc>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 3.0 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library.
|
||||
*/
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
/*
|
||||
* dphy_lane.v
|
||||
*
|
||||
* Implements a state and serdes control for a single lane of
|
||||
* the DSI link. Responsible for LP/HS-mode switching, serialization, trailing
|
||||
* sequences, LP data transmissions and many other things...
|
||||
*/
|
||||
|
||||
module dphy_lane
|
||||
(
|
||||
// system clock
|
||||
input clk_i,
|
||||
input rst_n_i,
|
||||
|
||||
// slow clock tick for timing LP transmissions
|
||||
input tick_i,
|
||||
|
||||
// High-speed mode TX interface
|
||||
|
||||
// requests transition to HS mode
|
||||
input hs_request_i,
|
||||
// indicates a valid HS byte to send
|
||||
input hs_valid_i,
|
||||
// HS byte to send
|
||||
input [7:0] hs_data_i,
|
||||
// HS mode data request
|
||||
output reg hs_ready_o,
|
||||
|
||||
// Low-power (Escape) mode TX interface
|
||||
// Requests LP mode
|
||||
input lp_request_i,
|
||||
// Low-power data word to be sent
|
||||
input [7:0] lp_data_i,
|
||||
// Strobe for lp_data_i
|
||||
input lp_valid_i,
|
||||
output reg lp_ready_o,
|
||||
|
||||
output reg idle_o,
|
||||
|
||||
// HS SerDes output
|
||||
output reg [7:0] serdes_data_o,
|
||||
output reg serdes_oe_o,
|
||||
|
||||
// LP buffer outputs
|
||||
output lp_txp_o,
|
||||
output lp_txn_o,
|
||||
output reg lp_oe_o
|
||||
);
|
||||
|
||||
// when true, the lane polarity (both HS and LP) is inverted. Useful for PCB design.
|
||||
parameter integer g_invert = 0;
|
||||
|
||||
`define LP_ACTIVE 0
|
||||
`define LP_POWERUP 1
|
||||
`define LP_REQUEST_LPDT0 2
|
||||
`define LP_REQUEST_LPDT1 3
|
||||
`define LP_REQUEST_LPDT2 4
|
||||
`define LP_REQUEST_LPDT3 5
|
||||
`define LP_WAIT_TX 6
|
||||
`define LP_START_TX 7
|
||||
`define LP_NEXT_BIT 8
|
||||
`define LP_MARK_BIT 9
|
||||
`define LP_EXIT0 10
|
||||
`define LP_EXIT1 11
|
||||
`define LP_SPACE 12
|
||||
`define LP_REQUEST_HS0 13
|
||||
`define LP_REQUEST_HS1 14
|
||||
`define LP_HS_ACTIVE 15
|
||||
`define LP_HS_EXIT0 16
|
||||
`define LP_HS_EXIT1 17
|
||||
`define LP_HS_EXIT2 23
|
||||
|
||||
reg lp_txp_int, lp_txn_int;
|
||||
|
||||
reg [4:0] lp_state;
|
||||
reg [7:0] lp_sreg;
|
||||
reg [3:0] tx_count;
|
||||
|
||||
reg lp_hs_entered;
|
||||
reg serdes_data_lastbit;
|
||||
|
||||
`define LP_TX(txp, txn, next_lp_state) \
|
||||
begin lp_oe_o <= 1;\
|
||||
lp_txp_int <= txp;\
|
||||
lp_txn_int <= txn;\
|
||||
if(tick_i)\
|
||||
lp_state <= next_lp_state; end
|
||||
|
||||
always@(posedge clk_i or negedge rst_n_i)
|
||||
begin
|
||||
if (!rst_n_i) begin
|
||||
lp_state <= `LP_ACTIVE;
|
||||
lp_txn_int <= 1;
|
||||
lp_txp_int <= 1;
|
||||
lp_oe_o <= 0;
|
||||
lp_hs_entered <= 0;
|
||||
lp_ready_o <= 0;
|
||||
idle_o <= 1;
|
||||
|
||||
end else begin
|
||||
case (lp_state)
|
||||
`LP_ACTIVE : begin
|
||||
lp_hs_entered <= 0;
|
||||
lp_oe_o <= 1;
|
||||
lp_txn_int <= 1;
|
||||
lp_txp_int <= 1;
|
||||
lp_ready_o <= 0;
|
||||
idle_o <= 1;
|
||||
|
||||
|
||||
if(tick_i) begin
|
||||
idle_o <= 0;
|
||||
|
||||
if(lp_request_i)
|
||||
lp_state <= `LP_REQUEST_LPDT0;
|
||||
else if(hs_request_i)
|
||||
lp_state <= `LP_REQUEST_HS0;
|
||||
else
|
||||
idle_o <= 1;
|
||||
end
|
||||
end // case: `LP_ACTIVE
|
||||
|
||||
`LP_REQUEST_HS0:
|
||||
`LP_TX(0,1,`LP_REQUEST_HS1)
|
||||
|
||||
`LP_REQUEST_HS1:
|
||||
`LP_TX(0,0,`LP_HS_ACTIVE)
|
||||
|
||||
`LP_HS_ACTIVE: begin
|
||||
lp_oe_o <= 0;
|
||||
lp_hs_entered <= 1;
|
||||
|
||||
if(!hs_request_i)
|
||||
lp_state <= `LP_HS_EXIT0;
|
||||
end
|
||||
|
||||
`LP_HS_EXIT0:
|
||||
if(tick_i) begin
|
||||
lp_txn_int <= 1;
|
||||
lp_txp_int <= 1;
|
||||
lp_state <= `LP_ACTIVE;
|
||||
end
|
||||
|
||||
`LP_HS_EXIT1:
|
||||
if(tick_i) begin
|
||||
lp_hs_entered <= 0;
|
||||
lp_state <= `LP_HS_EXIT2;
|
||||
end
|
||||
|
||||
`LP_HS_EXIT2: begin
|
||||
lp_oe_o <= 1;
|
||||
lp_txn_int <= 1;
|
||||
lp_txp_int <= 1;
|
||||
lp_hs_entered <= 0;
|
||||
lp_state <= `LP_ACTIVE;
|
||||
end
|
||||
|
||||
|
||||
`LP_REQUEST_LPDT0:
|
||||
`LP_TX(1,0,`LP_REQUEST_LPDT1)
|
||||
|
||||
`LP_REQUEST_LPDT1:
|
||||
`LP_TX(0,0,`LP_REQUEST_LPDT2)
|
||||
|
||||
`LP_REQUEST_LPDT2:
|
||||
`LP_TX(0,1,`LP_REQUEST_LPDT3)
|
||||
|
||||
`LP_REQUEST_LPDT3:
|
||||
`LP_TX(0,0,`LP_WAIT_TX)
|
||||
|
||||
`LP_WAIT_TX:
|
||||
lp_state <= `LP_START_TX;
|
||||
|
||||
`LP_START_TX: begin
|
||||
|
||||
if(!lp_request_i) begin
|
||||
lp_state <= `LP_EXIT0;
|
||||
lp_ready_o <= 0;
|
||||
|
||||
end else if (lp_valid_i) begin
|
||||
lp_sreg <= lp_data_i;
|
||||
lp_state <= `LP_NEXT_BIT;
|
||||
tx_count <= 8;
|
||||
lp_ready_o <= 0;
|
||||
|
||||
end else
|
||||
lp_ready_o <= 1;
|
||||
|
||||
end
|
||||
|
||||
`LP_NEXT_BIT: begin
|
||||
if(!tx_count)
|
||||
lp_state <= `LP_WAIT_TX;
|
||||
else if(tick_i) begin
|
||||
tx_count <= tx_count - 1;
|
||||
lp_txp_int<=lp_sreg[7] ;
|
||||
lp_txn_int<=~lp_sreg[7];
|
||||
lp_sreg <= lp_sreg << 1;
|
||||
lp_state <= `LP_MARK_BIT;
|
||||
end
|
||||
end // case: `LP_NEXT_BIT
|
||||
|
||||
`LP_MARK_BIT:
|
||||
if(tick_i)begin
|
||||
lp_txp_int <= 0;
|
||||
lp_txn_int <= 0;
|
||||
lp_state <= `LP_SPACE;
|
||||
end
|
||||
|
||||
`LP_SPACE:
|
||||
if(tick_i)begin
|
||||
lp_state <= `LP_NEXT_BIT;
|
||||
end
|
||||
|
||||
`LP_EXIT0:
|
||||
`LP_TX(1, 0, `LP_EXIT1)
|
||||
|
||||
`LP_EXIT1:
|
||||
`LP_TX(1, 1, `LP_ACTIVE)
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk_i)
|
||||
if(lp_state == `LP_HS_ACTIVE && hs_request_i && hs_valid_i)
|
||||
serdes_data_lastbit <= (g_invert ? ~hs_data_i[7] : hs_data_i[7]);
|
||||
|
||||
always@(hs_data_i, hs_valid_i, lp_hs_entered, lp_state, serdes_data_lastbit)
|
||||
begin
|
||||
// trailing sequence when exiting HS (inverse of last transmitted bit)
|
||||
if(lp_state == `LP_HS_EXIT0 || lp_state == `LP_HS_EXIT1 || lp_state == `LP_HS_EXIT2)
|
||||
serdes_data_o <= {8{~serdes_data_lastbit}};
|
||||
else if(hs_valid_i)
|
||||
serdes_data_o <= (g_invert ? ~hs_data_i : hs_data_i);
|
||||
// leading sequence (all 0's)
|
||||
else
|
||||
serdes_data_o <= (g_invert ? 8'hff:8'h00);
|
||||
serdes_oe_o <= lp_hs_entered;
|
||||
end
|
||||
|
||||
assign lp_txp_o = (g_invert ? lp_txn_int : lp_txp_int);
|
||||
assign lp_txn_o = (g_invert ? lp_txp_int : lp_txn_int);
|
||||
|
||||
always@(posedge clk_i)
|
||||
if(!rst_n_i)
|
||||
hs_ready_o <= 0;
|
||||
else if(tick_i && lp_hs_entered)
|
||||
hs_ready_o <= 1;
|
||||
else if(!hs_request_i)
|
||||
hs_ready_o <= 0;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,248 @@
|
|||
// file: dphy_serdes.v
|
||||
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "dphy_serdes,selectio_wiz_v3_2,{component_name=dphy_serdes,bus_dir=OUTPUTS,bus_sig_type=DIFF,bus_io_std=LVDS_25,use_serialization=true,use_phase_detector=false,serialization_factor=8,enable_bitslip=false,enable_train=false,system_data_width=3,bus_in_delay=NONE,bus_out_delay=NONE,clk_sig_type=SINGLE,clk_io_std=LVCMOS18,clk_buf=BUFPLL,active_edge=RISING,clk_delay=NONE,v6_bus_in_delay=NONE,v6_bus_out_delay=NONE,v6_clk_buf=BUFIO,v6_active_edge=NOT_APP,v6_ddr_alignment=SAME_EDGE_PIPELINED,v6_oddr_alignment=SAME_EDGE,ddr_alignment=C0,v6_interface_type=NETWORKING,interface_type=NETWORKING,v6_bus_in_tap=0,v6_bus_out_tap=0,v6_clk_io_std=LVCMOS18,v6_clk_sig_type=DIFF}" *)
|
||||
|
||||
module dphy_serdes
|
||||
// width of the data for the system
|
||||
#(parameter sys_w = 3,
|
||||
// width of the data for the device
|
||||
parameter dev_w = 24)
|
||||
(
|
||||
// From the device out to the system
|
||||
input [dev_w-1:0] DATA_OUT_FROM_DEVICE,
|
||||
output [sys_w-1:0] DATA_OUT_TO_PINS_P,
|
||||
output [sys_w-1:0] DATA_OUT_TO_PINS_N,
|
||||
input CLK_IN, // Fast clock input from PLL/MMCM
|
||||
input CLK_DIV_IN, // Slow clock input from PLL/MMCM
|
||||
input LOCKED_IN,
|
||||
output LOCKED_OUT,
|
||||
input CLK_RESET,
|
||||
input IO_RESET,
|
||||
input [sys_w-1:0] OE);
|
||||
|
||||
localparam num_serial_bits = dev_w/sys_w;
|
||||
// Signal declarations
|
||||
////------------------------------
|
||||
wire clock_enable = 1'b1;
|
||||
// Before the buffer
|
||||
wire [sys_w-1:0] data_out_to_pins_int;
|
||||
// Between the delay and serdes
|
||||
wire [sys_w-1:0] data_out_to_pins_predelay;
|
||||
// Array to use intermediately from the serdes to the internal
|
||||
// devices. bus "0" is the leftmost bus
|
||||
wire [sys_w-1:0] oserdes_d[0:7]; // fills in starting with 7
|
||||
// Create the clock logic
|
||||
BUFPLL
|
||||
#(.DIVIDE (8))
|
||||
bufpll_inst
|
||||
(.IOCLK (clk_in_int_buf),
|
||||
.LOCK (LOCKED_OUT),
|
||||
.SERDESSTROBE (serdesstrobe),
|
||||
.GCLK (CLK_DIV_IN), // GCLK must be driven by BUFG
|
||||
.LOCKED (LOCKED_IN),
|
||||
.PLLIN (CLK_IN));
|
||||
|
||||
// We have multiple bits- step over every bit, instantiating the required elements
|
||||
genvar pin_count;
|
||||
genvar slice_count;
|
||||
|
||||
wire [sys_w-1:0] oe_int_n;
|
||||
wire [sys_w-1:0] tq_out;
|
||||
|
||||
|
||||
generate for (pin_count = 0; pin_count < sys_w; pin_count = pin_count + 1) begin: pins
|
||||
// Instantiate the buffers
|
||||
////------------------------------
|
||||
// Instantiate a buffer for every bit of the data bus
|
||||
|
||||
OBUFTDS
|
||||
#(.IOSTANDARD ("DIFF_SSTL2_II"))
|
||||
obufds_inst
|
||||
(.O (DATA_OUT_TO_PINS_P [pin_count]),
|
||||
.OB (DATA_OUT_TO_PINS_N [pin_count]),
|
||||
.T (tq_out[pin_count]),
|
||||
.I (data_out_to_pins_int[pin_count]));
|
||||
|
||||
// always@(posedge CLK_DIV_IN)
|
||||
assign oe_int_n[pin_count] = ~OE[pin_count];
|
||||
|
||||
// Instantiate the delay primitive
|
||||
////-------------------------------
|
||||
IODELAY2
|
||||
#(.DATA_RATE ("SDR"),
|
||||
.ODELAY_VALUE (pin_count != sys_w - 1 ? 100 : 0),
|
||||
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT"),
|
||||
.DELAY_SRC ("ODATAIN"),
|
||||
.SERDES_MODE ("NONE"),
|
||||
.SIM_TAPDELAY_VALUE (75))
|
||||
iodelay2_bus
|
||||
(
|
||||
// required datapath
|
||||
.T (1'b0),
|
||||
.DOUT (data_out_to_pins_int [pin_count]),
|
||||
.ODATAIN (data_out_to_pins_predelay[pin_count]),
|
||||
// inactive data connections
|
||||
.IDATAIN (1'b0),
|
||||
.TOUT (),
|
||||
.DATAOUT (),
|
||||
.DATAOUT2 (),
|
||||
// connect up the clocks
|
||||
.IOCLK0 (1'b0), // No calibration needed
|
||||
.IOCLK1 (1'b0), // No calibration needed
|
||||
// Tie of the variable delay programming
|
||||
.CLK (CLK_DIV_IN),
|
||||
.CAL (1'b0),
|
||||
.INC (1'b0),
|
||||
.CE (1'b0),
|
||||
.BUSY (),
|
||||
.RST (IO_RESET));
|
||||
// assign data_out_to_pins_int[pin_count] = data_out_to_pins_predelay[pin_count];
|
||||
|
||||
// Instantiate the serdes primitive
|
||||
////------------------------------
|
||||
// local wire only for use in this generate loop
|
||||
wire cascade_ms_d;
|
||||
wire cascade_ms_t;
|
||||
wire cascade_sm_d;
|
||||
wire cascade_sm_t;
|
||||
|
||||
// declare the oserdes
|
||||
OSERDES2
|
||||
#(.DATA_RATE_OQ ("SDR"),
|
||||
.DATA_RATE_OT ("SDR"),
|
||||
.TRAIN_PATTERN (0),
|
||||
.DATA_WIDTH (num_serial_bits),
|
||||
.SERDES_MODE ("MASTER"),
|
||||
.OUTPUT_MODE ("DIFFERENTIAL"))
|
||||
oserdes2_master
|
||||
(.D1 (oserdes_d[3][pin_count]),
|
||||
.D2 (oserdes_d[2][pin_count]),
|
||||
.D3 (oserdes_d[1][pin_count]),
|
||||
.D4 (oserdes_d[0][pin_count]),
|
||||
.T1 (oe_int_n[pin_count]),
|
||||
.T2 (oe_int_n[pin_count]),
|
||||
.T3 (oe_int_n[pin_count]),
|
||||
.T4 (oe_int_n[pin_count]),
|
||||
.SHIFTIN1 (1'b1),
|
||||
.SHIFTIN2 (1'b1),
|
||||
.SHIFTIN3 (cascade_sm_d),
|
||||
.SHIFTIN4 (cascade_sm_t),
|
||||
.SHIFTOUT1 (cascade_ms_d),
|
||||
.SHIFTOUT2 (cascade_ms_t),
|
||||
.SHIFTOUT3 (),
|
||||
.SHIFTOUT4 (),
|
||||
.TRAIN (1'b0),
|
||||
.OCE (clock_enable),
|
||||
.CLK0 (clk_in_int_buf),
|
||||
.CLK1 (1'b0),
|
||||
.CLKDIV (CLK_DIV_IN),
|
||||
.OQ (data_out_to_pins_predelay[pin_count]),
|
||||
.TQ (tq_out[pin_count]),
|
||||
.IOCE (serdesstrobe),
|
||||
.TCE (clock_enable),
|
||||
.RST (IO_RESET));
|
||||
|
||||
|
||||
OSERDES2
|
||||
#(.DATA_RATE_OQ ("SDR"),
|
||||
.DATA_RATE_OT ("SDR"),
|
||||
.DATA_WIDTH (num_serial_bits),
|
||||
.SERDES_MODE ("SLAVE"),
|
||||
.TRAIN_PATTERN (0),
|
||||
.OUTPUT_MODE ("DIFFERENTIAL"))
|
||||
oserdes2_slave
|
||||
(.D1 (oserdes_d[7][pin_count]),
|
||||
.D2 (oserdes_d[6][pin_count]),
|
||||
.D3 (oserdes_d[5][pin_count]),
|
||||
.D4 (oserdes_d[4][pin_count]),
|
||||
.T1 (oe_int_n[pin_count]),
|
||||
.T2 (oe_int_n[pin_count]),
|
||||
.T3 (oe_int_n[pin_count]),
|
||||
.T4 (oe_int_n[pin_count]),
|
||||
.SHIFTIN1 (cascade_ms_d),
|
||||
.SHIFTIN2 (cascade_ms_t),
|
||||
.SHIFTIN3 (1'b1),
|
||||
.SHIFTIN4 (1'b1),
|
||||
.SHIFTOUT1 (),
|
||||
.SHIFTOUT2 (),
|
||||
.SHIFTOUT3 (cascade_sm_d),
|
||||
.SHIFTOUT4 (cascade_sm_t),
|
||||
.TRAIN (1'b0),
|
||||
.OCE (clock_enable),
|
||||
.CLK0 (clk_in_int_buf),
|
||||
.CLK1 (1'b0),
|
||||
.CLKDIV (CLK_DIV_IN),
|
||||
.OQ (),
|
||||
.TQ (),
|
||||
.IOCE (serdesstrobe),
|
||||
.TCE (clock_enable),
|
||||
.RST (IO_RESET));
|
||||
// Concatenate the serdes outputs together. Keep the timesliced
|
||||
// bits together, and placing the earliest bits on the right
|
||||
// ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
|
||||
// the output will be 3210, 7654, ...
|
||||
////---------------------------------------------------------
|
||||
for (slice_count = 0; slice_count < num_serial_bits; slice_count = slice_count + 1) begin: out_slices
|
||||
// This places the first data in time on the right
|
||||
assign oserdes_d[8-slice_count-1] =
|
||||
DATA_OUT_FROM_DEVICE[slice_count*sys_w+:sys_w];
|
||||
// To place the first data in time on the left, use the
|
||||
// following code, instead
|
||||
// assign oserdes_d[slice_count] =
|
||||
// DATA_OUT_FROM_DEVICE[slice_count*sys_w+:sys_w];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,455 @@
|
|||
/*
|
||||
* DSI Core
|
||||
* Copyright (C) 2013 twl <twlostow@printf.cc>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 3.0 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library.
|
||||
*/
|
||||
|
||||
`include "dsi_defs.vh"
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
/*
|
||||
* dsi_core.v
|
||||
*
|
||||
* Top level of the core. Currently works on Spartan-6 FPGAs only.
|
||||
*/
|
||||
|
||||
|
||||
module dsi_core
|
||||
(
|
||||
// system clock (= pixel clock for the moment)
|
||||
clk_sys_i,
|
||||
// PHY serdes clock (= 8x pixel clock)
|
||||
clk_phy_i,
|
||||
|
||||
rst_n_i,
|
||||
|
||||
pll_locked_i,
|
||||
|
||||
frame_ready_o,
|
||||
|
||||
// Pixel FIFO interface
|
||||
fifo_full_o,
|
||||
fifo_pixels_i,
|
||||
fifo_frame_i,
|
||||
fifo_wr_i,
|
||||
|
||||
// DSI high speed output (OSERDES2)
|
||||
dsi_hs_p_o,
|
||||
dsi_hs_n_o,
|
||||
|
||||
// DSI low power output
|
||||
dsi_lp_p_o,
|
||||
dsi_lp_n_o,
|
||||
|
||||
// Lop power output enable
|
||||
dsi_lp_oe_o,
|
||||
|
||||
// DSI clock lane output
|
||||
dsi_clk_p_o,
|
||||
dsi_clk_n_o,
|
||||
|
||||
// DSI clock lane LP signals + output enable
|
||||
dsi_clk_lp_p_o,
|
||||
dsi_clk_lp_n_o,
|
||||
dsi_clk_lp_oe_o,
|
||||
|
||||
// Displat reset pin
|
||||
dsi_reset_n_o,
|
||||
|
||||
// Host control registers
|
||||
host_a_i,
|
||||
host_d_i,
|
||||
host_d_o,
|
||||
host_wr_i
|
||||
);
|
||||
|
||||
parameter g_pixels_per_clock = 1;
|
||||
parameter g_lanes = 3;
|
||||
parameter g_fifo_size = 1024;
|
||||
parameter g_invert_lanes = 0;
|
||||
parameter g_invert_clock = 0;
|
||||
|
||||
localparam g_pixel_width = 24 * g_pixels_per_clock;
|
||||
|
||||
input clk_sys_i, clk_phy_i, rst_n_i;
|
||||
input pll_locked_i;
|
||||
output frame_ready_o;
|
||||
|
||||
|
||||
output fifo_full_o;
|
||||
input [g_pixel_width - 1 : 0 ] fifo_pixels_i;
|
||||
input fifo_frame_i, fifo_wr_i;
|
||||
|
||||
output dsi_clk_p_o, dsi_clk_n_o;
|
||||
output [g_lanes-1:0] dsi_hs_p_o, dsi_hs_n_o;
|
||||
output [g_lanes-1:0] dsi_lp_p_o, dsi_lp_n_o;
|
||||
output [g_lanes-1:0] dsi_lp_oe_o;
|
||||
|
||||
output dsi_clk_lp_p_o, dsi_clk_lp_n_o;
|
||||
output dsi_clk_lp_oe_o;
|
||||
|
||||
output reg dsi_reset_n_o;
|
||||
|
||||
input [5:0] host_a_i;
|
||||
input [31:0] host_d_i;
|
||||
output [31:0] host_d_o;
|
||||
input host_wr_i;
|
||||
|
||||
|
||||
///////////////////
|
||||
// PHY/Serdes layer
|
||||
///////////////////
|
||||
|
||||
reg tick = 0;
|
||||
|
||||
wire [g_lanes-1:0] phy_hs_ready_lane, lp_ready_lane, lp_readback_lane;
|
||||
wire [g_lanes:0] serdes_oe_lane;
|
||||
|
||||
|
||||
wire [g_lanes-1:0] lp_txp, lp_txn, lp_oe;
|
||||
|
||||
wire lp_ready;
|
||||
wire phy_hs_ready;
|
||||
|
||||
assign lp_ready = lp_ready_lane[0];
|
||||
assign phy_hs_ready = phy_hs_ready_lane[0];
|
||||
|
||||
wire phy_hs_request;
|
||||
wire [g_lanes * 8 -1 :0] phy_hs_data;
|
||||
wire [g_lanes-1:0] phy_hs_valid;
|
||||
wire [(g_lanes + 1) * 8 - 1: 0] serdes_data, serdes_data_interleaved;
|
||||
reg r_dsi_clk_en = 0;
|
||||
reg lp_request = 0;
|
||||
reg lp_valid = 0;
|
||||
reg [7:0] lp_data = 0;
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for(i=0;i<g_lanes;i=i+1)
|
||||
begin
|
||||
dphy_lane
|
||||
#(
|
||||
.g_invert(g_invert_lanes&(1<<i)?1:0)
|
||||
)
|
||||
U_LaneX
|
||||
(
|
||||
.clk_i(clk_sys_i),
|
||||
.rst_n_i(rst_n_i),
|
||||
|
||||
|
||||
.tick_i(tick),
|
||||
|
||||
.hs_request_i (phy_hs_request),
|
||||
.hs_data_i (phy_hs_data[ (g_lanes-i) *8-1 -:8]), // >> ((g_lanes - 1 - i)*8)}),
|
||||
.hs_ready_o (phy_hs_ready_lane[i]),
|
||||
.hs_valid_i(phy_hs_valid[i]),
|
||||
|
||||
.lp_request_i (lp_request),
|
||||
.lp_data_i (lp_data),
|
||||
.lp_valid_i (i ==0 ? lp_valid : 1'b0),
|
||||
.lp_ready_o (lp_ready_lane[i]),
|
||||
|
||||
.serdes_data_o(serdes_data[i*8+:8]),
|
||||
|
||||
.lp_txp_o(lp_txp[i]),
|
||||
.lp_txn_o(lp_txn[i]),
|
||||
.lp_oe_o(lp_oe[i])
|
||||
);
|
||||
|
||||
assign dsi_lp_p_o[i] = lp_txp[i];
|
||||
assign dsi_lp_n_o[i] = lp_txn[i];
|
||||
assign dsi_lp_oe_o[i] = lp_oe[0];
|
||||
assign serdes_oe_lane[i] = ~lp_oe[0];
|
||||
|
||||
end // for (i=0;i<g_lanes;i=i+1)
|
||||
endgenerate
|
||||
|
||||
wire clk_lane_ready;
|
||||
wire dsi_clk_lp_oe;
|
||||
|
||||
dphy_lane
|
||||
#(
|
||||
.g_invert(g_invert_clock)
|
||||
) U_ClockLane (
|
||||
.clk_i(clk_sys_i),
|
||||
.rst_n_i(rst_n_i),
|
||||
|
||||
|
||||
.tick_i(tick),
|
||||
|
||||
.hs_request_i (r_dsi_clk_en),
|
||||
.hs_data_i (clk_lane_ready ? 8'haa : 8'h00),
|
||||
.hs_ready_o (clk_lane_ready),
|
||||
.hs_valid_i(1'b1),
|
||||
|
||||
.lp_request_i (1'b0),
|
||||
.lp_data_i(8'h00),
|
||||
.lp_valid_i(1'b0),
|
||||
.lp_ready_o(),
|
||||
|
||||
.serdes_data_o(serdes_data[g_lanes*8+:8]),
|
||||
|
||||
.lp_txp_o(dsi_clk_lp_p_o),
|
||||
.lp_txn_o(dsi_clk_lp_n_o),
|
||||
.lp_oe_o(dsi_clk_lp_oe)
|
||||
);
|
||||
|
||||
assign serdes_oe_lane [g_lanes] = ~dsi_clk_lp_oe;
|
||||
assign dsi_clk_lp_oe_o = dsi_clk_lp_oe;
|
||||
|
||||
|
||||
generate
|
||||
genvar gi, gj;
|
||||
for(gi=0;gi<8;gi=gi+1)
|
||||
begin
|
||||
assign serdes_data_interleaved[(g_lanes+1)*gi+g_lanes] = serdes_data[8*g_lanes+gi];
|
||||
|
||||
for(gj=0;gj<g_lanes; gj=gj+1)
|
||||
begin
|
||||
assign serdes_data_interleaved[(g_lanes+1)*gi+gj] = serdes_data[8*gj+gi];
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
dphy_serdes
|
||||
#(
|
||||
.sys_w (g_lanes + 1) ,
|
||||
.dev_w (g_lanes * 8 + 8)
|
||||
) U_Serdes (
|
||||
.DATA_OUT_FROM_DEVICE(serdes_data_interleaved),
|
||||
.DATA_OUT_TO_PINS_P({dsi_clk_p_o, dsi_hs_p_o }),
|
||||
.DATA_OUT_TO_PINS_N({dsi_clk_n_o, dsi_hs_n_o }),
|
||||
.CLK_IN(clk_phy_i),
|
||||
.CLK_DIV_IN(clk_sys_i),
|
||||
.LOCKED_IN(pll_locked_i),
|
||||
.CLK_RESET(~rst_n_i),
|
||||
.IO_RESET(~rst_n_i),
|
||||
.OE(serdes_oe_lane));
|
||||
|
||||
////////////////
|
||||
// Packet layer
|
||||
///////////////
|
||||
|
||||
wire p_req, p_islong, p_dreq, p_last;
|
||||
wire [5:0] p_type;
|
||||
wire [15:0] p_command, p_wcount;
|
||||
wire [g_pixel_width-1:0] p_payload;
|
||||
|
||||
|
||||
dsi_packet_assembler
|
||||
#(
|
||||
.g_num_lanes(g_lanes),
|
||||
.g_bytes_per_clock(g_pixels_per_clock)
|
||||
) U_PktAsm (
|
||||
.clk_i(clk_sys_i),
|
||||
.rst_n_i(rst_n_i),
|
||||
|
||||
.p_req_i(p_req),
|
||||
.p_islong_i(p_islong),
|
||||
.p_type_i(p_type),
|
||||
.p_wcount_i(p_wcount),
|
||||
.p_command_i(p_command),
|
||||
.p_dreq_o(p_dreq),
|
||||
.p_dlast_o(p_dlast),
|
||||
.p_payload_i(p_payload),
|
||||
.p_last_i(p_last),
|
||||
|
||||
.phy_d_o(phy_hs_data),
|
||||
.phy_hs_request_o(phy_hs_request),
|
||||
.phy_hs_dreq_i(phy_hs_ready_lane[0]),
|
||||
.phy_dvalid_o(phy_hs_valid)
|
||||
);
|
||||
|
||||
////////////////
|
||||
// Test Screen generator
|
||||
///////////////
|
||||
|
||||
wire fifo_frame_tgen, fifo_wr_tgen;
|
||||
wire [g_pixel_width-1:0] fifo_pixel_tgen;
|
||||
|
||||
wire fifo_empty, fifo_rd;
|
||||
wire [g_pixel_width:0] fifo_dout;
|
||||
|
||||
wire fifo_frame_int, fifo_wr_int, fifo_full_int;
|
||||
wire [g_pixel_width-1:0] fifo_pixels_int;
|
||||
|
||||
wire tgen_enable;
|
||||
|
||||
dsi_test_image_gen
|
||||
U_TestImgGen
|
||||
(
|
||||
.clk_i(clk_sys_i),
|
||||
.rst_n_i(rst_n_i),
|
||||
|
||||
.fifo_full_i(fifo_full_int),
|
||||
.fifo_frame_o(fifo_frame_tgen),
|
||||
.fifo_pixel_o(fifo_pixel_tgen),
|
||||
.fifo_we_o(fifo_wr_tgen),
|
||||
|
||||
.host_a_i(host_a_i),
|
||||
.host_d_i(host_d_i),
|
||||
.host_wr_i(host_wr_i),
|
||||
.test_enable_o(tgen_enable)
|
||||
);
|
||||
|
||||
|
||||
assign fifo_frame_int = (tgen_enable ? fifo_frame_tgen : fifo_frame_i);
|
||||
assign fifo_pixels_int = (tgen_enable ? fifo_pixel_tgen : fifo_pixels_i);
|
||||
assign fifo_wr_int = (tgen_enable ? fifo_wr_tgen : fifo_wr_i);
|
||||
|
||||
assign fifo_full_o = fifo_full_int;
|
||||
|
||||
reg fifo_rd_d0, fifo_got_frame;
|
||||
|
||||
///////////////
|
||||
// Image timing
|
||||
///////////////
|
||||
|
||||
dsi_timing_gen U_TimingGen
|
||||
(
|
||||
.clk_i(clk_sys_i),
|
||||
.rst_n_i(rst_n_i),
|
||||
|
||||
.fifo_empty_i(fifo_empty),
|
||||
.fifo_rd_o(fifo_rd),
|
||||
.fifo_pixels_i(fifo_dout[g_pixel_width-1:0]),
|
||||
.fifo_frame_i(fifo_dout[g_pixel_width]),
|
||||
.fifo_got_frame_i(fifo_got_frame),
|
||||
.p_req_o(p_req),
|
||||
.p_islong_o(p_islong),
|
||||
.p_type_o(p_type),
|
||||
.p_wcount_o(p_wcount),
|
||||
.p_command_o(p_command),
|
||||
.p_payload_o(p_payload),
|
||||
.p_dreq_i(p_dreq),
|
||||
.p_last_o(p_last),
|
||||
|
||||
.host_a_i(host_a_i),
|
||||
.host_d_i(host_d_i),
|
||||
// .host_d_o(host_d_o),
|
||||
.host_wr_i(host_wr_i)
|
||||
);
|
||||
|
||||
|
||||
////////////////
|
||||
/// Pixel Buffer
|
||||
////////////////
|
||||
|
||||
dsi_fifo #(
|
||||
.g_width(g_pixel_width + 1),
|
||||
.g_size(g_fifo_size)
|
||||
) U_PixFifo (
|
||||
.clk_i(clk_sys_i),
|
||||
.rst_n_i(rst_n_i),
|
||||
.d_i({fifo_frame_int, fifo_pixels_int}),
|
||||
.we_i(fifo_wr_int),
|
||||
.full_o(fifo_full_int),
|
||||
.q_o(fifo_dout),
|
||||
.rd_i(fifo_rd),
|
||||
.empty_o(fifo_empty)
|
||||
);
|
||||
|
||||
|
||||
always@(posedge clk_sys_i)
|
||||
if(!rst_n_i)
|
||||
begin
|
||||
fifo_rd_d0 <= 0;
|
||||
fifo_got_frame <= 0;
|
||||
end else begin
|
||||
fifo_rd_d0 <= fifo_rd;
|
||||
|
||||
if(fifo_wr_int && fifo_frame_int)
|
||||
fifo_got_frame <= 1;
|
||||
else if (fifo_rd && fifo_dout[g_pixel_width])
|
||||
fifo_got_frame <= 0;
|
||||
end // else: !if(!rst_n_i)
|
||||
|
||||
|
||||
|
||||
////////////////
|
||||
// Host regs
|
||||
////////////////
|
||||
|
||||
reg [11:0] r_tick_div, tick_count;
|
||||
|
||||
|
||||
always@(posedge clk_sys_i)
|
||||
begin
|
||||
if (!rst_n_i)
|
||||
tick_count <= 0;
|
||||
else begin
|
||||
if(tick_count == r_tick_div)
|
||||
begin
|
||||
tick <= 1;
|
||||
tick_count <= 0;
|
||||
end else begin
|
||||
tick <= 0;
|
||||
tick_count <= tick_count + 1;
|
||||
end
|
||||
end // else: !if(!rst_n_i)
|
||||
end // always@ (posedge clk_sys_i)
|
||||
|
||||
reg [31:0] host_d_self;
|
||||
|
||||
always@(posedge clk_sys_i)
|
||||
if(!rst_n_i)
|
||||
begin
|
||||
r_tick_div <= 0;
|
||||
r_dsi_clk_en <= 0;
|
||||
lp_request <= 0;
|
||||
host_d_self <= 0;
|
||||
dsi_reset_n_o <= 0;
|
||||
end else if(host_wr_i) begin
|
||||
case(host_a_i)
|
||||
`REG_TICK_DIV: r_tick_div <= host_d_i;
|
||||
`REG_DSI_CTL: begin
|
||||
r_dsi_clk_en <= host_d_i[0];
|
||||
lp_request <= host_d_i[1];
|
||||
end
|
||||
|
||||
`REG_LP_TX:
|
||||
if(lp_ready) begin
|
||||
lp_valid <= host_d_i[8];
|
||||
lp_data <= host_d_i[7:0];
|
||||
end
|
||||
`REG_GPIO: begin
|
||||
dsi_reset_n_o <= host_d_i[0];
|
||||
end
|
||||
|
||||
endcase // case (host_a_i)
|
||||
end else begin
|
||||
lp_valid <= 0;
|
||||
|
||||
case(host_a_i)
|
||||
`REG_DSI_CTL: begin
|
||||
host_d_self[0] <= r_dsi_clk_en;
|
||||
host_d_self[31:2] <= 0;
|
||||
host_d_self[1] <= lp_ready;
|
||||
end
|
||||
|
||||
default:
|
||||
host_d_self <= 0;
|
||||
endcase // case (host_a_i)
|
||||
end // else: !if(host_wr_i)
|
||||
|
||||
assign host_d_o = host_d_self;
|
||||
|
||||
endmodule // dsi_core
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* DSI Core
|
||||
* Copyright (C) 2013 twl <twlostow@printf.cc>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 3.0 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library.
|
||||
*/
|
||||
|
||||
`define PTYPE_VSYNC_START 6'h1
|
||||
`define PTYPE_VSYNC_END 6'h11
|
||||
`define PTYPE_HSYNC_START 6'h21
|
||||
`define PTYPE_HSYNC_END 6'h31
|
||||
|
||||
`define PTYPE_BLANKING 6'h19
|
||||
`define PTYPE_RGB24 6'h3e
|
||||
|
||||
`define DSI_SYNC_SEQ 8'b10111000
|
||||
|
||||
`define REG_H_FRONT_PORCH 0
|
||||
`define REG_H_BACK_PORCH 1
|
||||
`define REG_H_ACTIVE 2
|
||||
`define REG_H_TOTAL 3
|
||||
|
||||
`define REG_V_FRONT_PORCH 4
|
||||
`define REG_V_BACK_PORCH 5
|
||||
`define REG_V_ACTIVE 6
|
||||
`define REG_V_TOTAL 7
|
||||
|
||||
`define REG_TIMING_CTL 8
|
||||
`define REG_TICK_DIV 9
|
||||
`define REG_DSI_CTL 10
|
||||
|
||||
`define REG_TEST_XSIZE 11
|
||||
`define REG_TEST_YSIZE 12
|
||||
`define REG_TEST_CTL 13
|
||||
`define REG_LP_TX 14
|
||||
`define REG_GPIO 15
|
||||
|
||||
`define REG_DBG_WADDR 16
|
||||
`define REG_DBG_RADDR 17
|
||||
`define REG_DBG_DATA 19
|
||||
`define REG_DBG_CTL 20
|
||||
|
||||
`define DBG_CTL_SEND 1
|
||||
`define DBG_CTL_NEXT 2
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
/*
|
||||
* DSI Core
|
||||
* Copyright (C) 2013 twl <twlostow@printf.cc>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 3.0 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library.
|
||||
*/
|
||||
|
||||
`timescale 1ns/1ns
|
||||
|
||||
/*
|
||||
* dsi_fifo.v
|
||||
*
|
||||
* Simple synchronous FIFO.
|
||||
*/
|
||||
|
||||
module dsi_fifo
|
||||
#(
|
||||
parameter g_width = 32,
|
||||
parameter g_size = 1024
|
||||
) (
|
||||
input clk_i,
|
||||
input rst_n_i,
|
||||
|
||||
input [g_width-1:0] d_i,
|
||||
input we_i,
|
||||
output full_o,
|
||||
|
||||
output reg [g_width-1:0] q_o,
|
||||
input rd_i,
|
||||
output empty_o
|
||||
);
|
||||
function integer CLogB2;
|
||||
input [31:0] Depth;
|
||||
integer i;
|
||||
begin
|
||||
i = Depth;
|
||||
for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
|
||||
i = i >> 1;
|
||||
end
|
||||
endfunction // for
|
||||
|
||||
localparam c_bits = CLogB2(g_size) - 1;
|
||||
|
||||
reg [c_bits-1:0] rd_ptr, wr_ptr;
|
||||
reg [c_bits:0] usedw;
|
||||
|
||||
wire [c_bits-1:0] mem_rd_addr;
|
||||
reg full, empty;
|
||||
reg guard_bit;
|
||||
|
||||
always@(posedge clk_i)
|
||||
if(!rst_n_i)
|
||||
begin
|
||||
rd_ptr <= 0;
|
||||
wr_ptr <= 0;
|
||||
end else begin
|
||||
if(we_i && !full)
|
||||
wr_ptr<=wr_ptr+1;
|
||||
if(rd_i && !empty)
|
||||
rd_ptr<=rd_ptr+1;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk_i)
|
||||
if(!rst_n_i)
|
||||
usedw <= 0;
|
||||
else begin
|
||||
if (we_i && !rd_i && !full)
|
||||
usedw<=usedw+1;
|
||||
else if (!we_i && rd_i &&!empty)
|
||||
usedw <= usedw - 1;
|
||||
end
|
||||
|
||||
always@(posedge clk_i)
|
||||
if(!rst_n_i)
|
||||
begin
|
||||
full <= 0;
|
||||
empty <= 1;
|
||||
end else begin
|
||||
if (usedw == 1 && rd_i && !we_i)
|
||||
empty <= 1;
|
||||
else if(we_i && !rd_i)
|
||||
empty <= 0;
|
||||
|
||||
if(usedw == g_size-2 && we_i && !rd_i)
|
||||
full <= 1;
|
||||
else if(usedw == g_size-1 && rd_i && !we_i)
|
||||
full <= 0;
|
||||
end // else: !if(!rst_n_i)
|
||||
|
||||
|
||||
assign full_o = full;
|
||||
assign empty_o = empty;
|
||||
|
||||
reg [g_width-1:0] mem[0:g_size-1];
|
||||
|
||||
assign mem_rd_addr = rd_i ? rd_ptr : (rd_ptr - 1);
|
||||
|
||||
always@(posedge clk_i)
|
||||
begin
|
||||
q_o <= mem[mem_rd_addr];
|
||||
if(we_i)
|
||||
mem[wr_ptr] <= d_i;
|
||||
end
|
||||
|
||||
// synthesis translate_off
|
||||
initial begin : init_contents
|
||||
integer i;
|
||||
|
||||
for(i=0;i<g_size;i=i+1)
|
||||
mem[i] = 0;
|
||||
|
||||
end
|
||||
// synthesis translate_on
|
||||
|
||||
|
||||
endmodule // dsi_fifo
|
||||
|
|
@ -0,0 +1,238 @@
|
|||
/*
|
||||
* DSI Core
|
||||
* Copyright (C) 2013 twl <twlostow@printf.cc>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 3.0 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library.
|
||||
*/
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
/*
|
||||
* dsi_packer.v
|
||||
*
|
||||
* A module that tightly packs bytes or byte sequences in to an output word of certain
|
||||
* size.
|
||||
*/
|
||||
|
||||
module dsi_byte_reverse
|
||||
(
|
||||
d_i,
|
||||
q_o);
|
||||
parameter g_num_bytes = 4;
|
||||
|
||||
input [g_num_bytes * 8 - 1 : 0] d_i;
|
||||
output [g_num_bytes * 8 - 1 : 0] q_o;
|
||||
|
||||
generate
|
||||
genvar i, j;
|
||||
for(i=0;i<8;i=i+1)
|
||||
for(j=0;j<g_num_bytes;j=j+1)
|
||||
assign q_o[8 * (g_num_bytes-1-j) + i] = d_i[8 * j + i];
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
module dsi_byte_swapper
|
||||
(
|
||||
d_i,
|
||||
size_i,
|
||||
q_o);
|
||||
|
||||
parameter g_num_bytes = 4;
|
||||
|
||||
input [g_num_bytes * 8 - 1 : 0] d_i;
|
||||
output [g_num_bytes * 8 - 1 : 0] q_o;
|
||||
input [2:0] size_i;
|
||||
|
||||
|
||||
wire [g_num_bytes * 8 - 1 : 0] swapped[1:g_num_bytes];
|
||||
|
||||
generate
|
||||
genvar i, j, nbytes;
|
||||
for(nbytes = 1; nbytes <= g_num_bytes; nbytes = nbytes + 1)
|
||||
for(i=0;i<8;i=i+1)
|
||||
begin
|
||||
for(j=0;j<nbytes;j=j+1)
|
||||
assign swapped[nbytes] [8 * (nbytes-1-j) + i] = d_i[8 * j + i];
|
||||
for(j=nbytes;j<g_num_bytes;j=j+1)
|
||||
assign swapped[nbytes] [j * 8 + i ] = 1'b0;
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
|
||||
assign q_o = (size_i) <= g_num_bytes ? swapped[size_i] : 'hx;
|
||||
endmodule
|
||||
|
||||
module dsi_byte_shifter
|
||||
(
|
||||
d_i,
|
||||
shifted_o,
|
||||
shift_i
|
||||
);
|
||||
|
||||
parameter g_data_bytes = 3;
|
||||
parameter g_max_shift = 3;
|
||||
|
||||
localparam c_output_width = 8 * (g_data_bytes + g_max_shift);
|
||||
|
||||
input [3:0] shift_i;
|
||||
input [g_data_bytes * 8 - 1: 0] d_i;
|
||||
output [c_output_width - 1: 0] shifted_o;
|
||||
|
||||
wire [c_output_width - 1 : 0] gen_array[0:g_max_shift];
|
||||
|
||||
genvar i;
|
||||
|
||||
generate
|
||||
for (i=0;i<g_max_shift;i=i+1)
|
||||
assign gen_array[i] = d_i << (i * 8);
|
||||
endgenerate
|
||||
|
||||
assign shifted_o = gen_array[shift_i];
|
||||
endmodule // dsi_byte_shifter
|
||||
|
||||
module dsi_packer
|
||||
(
|
||||
clk_i,
|
||||
rst_n_i,
|
||||
|
||||
d_i,
|
||||
d_size_i,
|
||||
d_req_o,
|
||||
d_valid_i,
|
||||
d_empty_o,
|
||||
|
||||
q_o,
|
||||
q_req_i,
|
||||
q_flush_i,
|
||||
q_valid_o
|
||||
);
|
||||
|
||||
|
||||
parameter g_input_bytes = 3;
|
||||
parameter g_output_bytes = 3;
|
||||
|
||||
|
||||
localparam c_shiftreg_bytes = 2 * (g_input_bytes > g_output_bytes ? g_input_bytes : g_output_bytes) + 2;
|
||||
|
||||
|
||||
input clk_i, rst_n_i;
|
||||
input [g_input_bytes * 8 - 1 : 0] d_i;
|
||||
input [3 : 0] d_size_i;
|
||||
output d_req_o;
|
||||
input d_valid_i, q_flush_i;
|
||||
|
||||
output [g_output_bytes * 8 -1 :0] q_o;
|
||||
output reg [g_output_bytes-1:0] q_valid_o;
|
||||
output d_empty_o;
|
||||
|
||||
input q_req_i;
|
||||
|
||||
wire [g_input_bytes * 8 - 1 : 0] d_in;
|
||||
reg [g_output_bytes * 8 - 1 : 0] q_out;
|
||||
|
||||
reg [4:0] count, avail, avail_next;
|
||||
reg [c_shiftreg_bytes * 8 -1 :0] shreg;
|
||||
wire [c_shiftreg_bytes * 8 -1 :0] in_shifted;
|
||||
wire shift_out;
|
||||
wire [4:0] in_shift;
|
||||
|
||||
wire d_req_int;
|
||||
|
||||
|
||||
assign shift_out = (count >= g_output_bytes && q_req_i);
|
||||
assign in_shift = (shift_out ? count - g_output_bytes : count);
|
||||
|
||||
|
||||
dsi_byte_swapper #(g_input_bytes) U_RevIn ( d_i, d_size_i, d_in );
|
||||
dsi_byte_reverse #(g_output_bytes) U_RevOut ( q_out, q_o );
|
||||
|
||||
|
||||
|
||||
dsi_byte_shifter
|
||||
#(
|
||||
.g_data_bytes(g_input_bytes),
|
||||
.g_max_shift(c_shiftreg_bytes - 1)
|
||||
)
|
||||
U_Shifter
|
||||
(
|
||||
.d_i(d_in),
|
||||
.shift_i(in_shift),
|
||||
.shifted_o(in_shifted)
|
||||
);
|
||||
|
||||
|
||||
always@(posedge clk_i)
|
||||
if(!rst_n_i) begin
|
||||
q_valid_o <= 0;
|
||||
q_out <= 0;
|
||||
end else if(shift_out || q_flush_i)
|
||||
begin : drive_output
|
||||
integer i;
|
||||
|
||||
q_out <= shreg[g_output_bytes * 8 - 1 : 0];
|
||||
for(i=0;i<g_output_bytes;i=i+1)
|
||||
q_valid_o[i] <= count > i;
|
||||
end else
|
||||
q_valid_o <= 0;
|
||||
|
||||
|
||||
always@(posedge clk_i)
|
||||
if (!rst_n_i)
|
||||
begin
|
||||
count <= 0;
|
||||
avail <= c_shiftreg_bytes;
|
||||
shreg <= 0;
|
||||
|
||||
end else begin
|
||||
if(d_valid_i && shift_out) begin
|
||||
shreg <= (shreg >> ( 8 * g_output_bytes )) | in_shifted;
|
||||
count <= count - g_output_bytes + d_size_i;
|
||||
end else if(d_valid_i) begin
|
||||
shreg <= shreg | in_shifted;
|
||||
count <= count + d_size_i;
|
||||
end else if(shift_out) begin
|
||||
shreg <= (shreg >> ( 8 * g_output_bytes ));
|
||||
count <= count - g_output_bytes;
|
||||
end else if (q_flush_i) begin
|
||||
count <= 0;
|
||||
shreg <= 0;
|
||||
end
|
||||
avail <= avail_next;
|
||||
end // else: !if(!rst_n_i)
|
||||
|
||||
|
||||
always@*
|
||||
if(d_valid_i && shift_out)
|
||||
avail_next <= avail + g_output_bytes - d_size_i;
|
||||
else if(d_valid_i)
|
||||
avail_next <= avail - d_size_i;
|
||||
else if(shift_out)
|
||||
avail_next <= avail + g_output_bytes;
|
||||
else if(q_flush_i)
|
||||
avail_next <= c_shiftreg_bytes;
|
||||
else
|
||||
avail_next <= avail;
|
||||
|
||||
|
||||
assign d_req_int = (avail_next >= g_input_bytes) || (shift_out && avail_next >= (g_input_bytes - g_output_bytes));
|
||||
assign d_req_o = d_req_int;
|
||||
assign d_empty_o = !count;
|
||||
|
||||
|
||||
endmodule // dsi_packer
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,264 @@
|
|||
/*
|
||||
* DSI Core
|
||||
* Copyright (C) 2013 twl <twlostow@printf.cc>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 3.0 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library.
|
||||
*/
|
||||
|
||||
|
||||
`include "dsi_defs.vh"
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
/*
|
||||
* dsi_packet_assembler.v
|
||||
*
|
||||
* Puts together DSI packets and produces a packed data stream for the PHY.
|
||||
*/
|
||||
|
||||
module dsi_packet_assembler
|
||||
(
|
||||
clk_i,
|
||||
rst_n_i,
|
||||
p_req_i,
|
||||
p_islong_i,
|
||||
p_type_i,
|
||||
p_wcount_i,
|
||||
p_command_i,
|
||||
p_payload_i,
|
||||
p_dreq_o,
|
||||
p_dlast_o,
|
||||
p_last_i,
|
||||
|
||||
phy_d_o,
|
||||
phy_dvalid_o,
|
||||
phy_hs_request_o,
|
||||
phy_hs_dreq_i
|
||||
);
|
||||
|
||||
parameter g_bytes_per_clock = 1;
|
||||
parameter g_num_lanes = 3;
|
||||
|
||||
input clk_i;
|
||||
input rst_n_i;
|
||||
|
||||
input p_req_i;
|
||||
input p_islong_i;
|
||||
input [5:0] p_type_i;
|
||||
input [15:0] p_wcount_i;
|
||||
input [15:0] p_command_i;
|
||||
input [g_bytes_per_clock * 24-1:0] p_payload_i;
|
||||
input p_last_i;
|
||||
|
||||
output p_dreq_o;
|
||||
output p_dlast_o;
|
||||
output [g_num_lanes*8-1:0] phy_d_o;
|
||||
output [g_num_lanes-1:0] phy_dvalid_o;
|
||||
|
||||
output phy_hs_request_o;
|
||||
input phy_hs_dreq_i;
|
||||
|
||||
`define ST_LP_MODE 3
|
||||
`define ST_IDLE 0
|
||||
`define ST_PAYLOAD 1
|
||||
`define ST_CRC 2
|
||||
|
||||
reg [3:0] state;
|
||||
reg [15:0] tx_count;
|
||||
wire [15:0] tx_count_next;
|
||||
|
||||
reg [31:0] pack_data;
|
||||
wire pack_req;
|
||||
reg pack_req_d0;
|
||||
|
||||
reg [3:0] pack_size;
|
||||
reg pack_valid;
|
||||
wire pack_empty;
|
||||
reg pack_flush;
|
||||
wire [g_num_lanes-1:0] pack_qvalid;
|
||||
|
||||
assign tx_count_next = tx_count - 3;
|
||||
|
||||
dsi_packer
|
||||
#(
|
||||
.g_input_bytes(4*g_bytes_per_clock),
|
||||
.g_output_bytes(g_num_lanes)
|
||||
)
|
||||
U_Packer
|
||||
(
|
||||
.clk_i(clk_i),
|
||||
.rst_n_i(rst_n_i),
|
||||
|
||||
.d_i(pack_data),
|
||||
.d_size_i(pack_size),
|
||||
.d_req_o(pack_req),
|
||||
.d_valid_i(pack_valid),
|
||||
.d_empty_o(pack_empty),
|
||||
|
||||
.q_o(phy_d_o),
|
||||
.q_req_i(phy_hs_dreq_i),
|
||||
.q_valid_o(pack_qvalid),
|
||||
.q_flush_i(pack_flush)
|
||||
);
|
||||
|
||||
|
||||
reg crc_reset,crc_valid;
|
||||
wire [15:0] crc_value;
|
||||
reg [2:0] crc_nbytes = 3;
|
||||
|
||||
dsi_crc
|
||||
#(
|
||||
.g_max_data_bytes(3)
|
||||
)
|
||||
U_CRC
|
||||
(
|
||||
.clk_i(clk_i),
|
||||
.rst_i(crc_reset),
|
||||
.valid_i(crc_valid),
|
||||
.nbytes_i(crc_nbytes),
|
||||
.d_i(p_payload_i),
|
||||
.crc_o(crc_value)
|
||||
);
|
||||
|
||||
|
||||
reg [23:0] pack_header;
|
||||
wire [23:0] pack_header_swapped;
|
||||
|
||||
wire [7:0] ecc_value;
|
||||
|
||||
always @*
|
||||
if(p_islong_i)
|
||||
pack_header <= { 2'b00, p_type_i, p_wcount_i[7:0], p_wcount_i[15:8] };
|
||||
else
|
||||
pack_header <= { 2'b00, p_type_i, p_command_i[7:0], p_command_i[15:8] };
|
||||
|
||||
assign pack_header_swapped [7:0] = pack_header[23:16];
|
||||
assign pack_header_swapped [15:8] = pack_header[15:8];
|
||||
assign pack_header_swapped [23:16] = pack_header[7:0];
|
||||
|
||||
|
||||
dsi_parity U_ECC
|
||||
(
|
||||
.d_i(pack_header_swapped),
|
||||
.p_o(ecc_value)
|
||||
);
|
||||
|
||||
|
||||
always @*
|
||||
begin
|
||||
crc_valid <= (state == `ST_PAYLOAD ? pack_req_d0 : 0);
|
||||
crc_reset <= (state == `ST_IDLE ? 1: 0 );
|
||||
end
|
||||
|
||||
assign p_idle_o = (state == `ST_IDLE || state == `ST_LP_MODE);
|
||||
|
||||
always@(posedge clk_i)
|
||||
pack_req_d0 <= pack_req;
|
||||
|
||||
|
||||
always@(posedge clk_i)
|
||||
if(!rst_n_i) begin
|
||||
state <= `ST_LP_MODE;
|
||||
end else begin
|
||||
case (state)
|
||||
`ST_LP_MODE:
|
||||
if(p_req_i && pack_req_d0 && phy_hs_dreq_i) begin
|
||||
state <= `ST_IDLE;
|
||||
end
|
||||
|
||||
`ST_IDLE: begin
|
||||
tx_count <=0;
|
||||
|
||||
if(p_req_i && pack_req_d0) begin
|
||||
|
||||
tx_count <= p_wcount_i;
|
||||
|
||||
if(p_islong_i)
|
||||
state <= `ST_PAYLOAD;
|
||||
else begin
|
||||
if(p_last_i)
|
||||
state <= `ST_LP_MODE;
|
||||
else
|
||||
state <= `ST_IDLE;
|
||||
end
|
||||
end else if(!p_req_i)
|
||||
state <= `ST_LP_MODE;
|
||||
|
||||
end // case: `ST_IDLE
|
||||
|
||||
`ST_PAYLOAD:
|
||||
if(pack_req_d0)
|
||||
begin
|
||||
tx_count <= tx_count_next;
|
||||
|
||||
if(!tx_count_next)
|
||||
state <= `ST_CRC;
|
||||
else if(!p_req_i)
|
||||
state <= `ST_LP_MODE;
|
||||
end
|
||||
|
||||
`ST_CRC:
|
||||
if(pack_req_d0) begin
|
||||
state <= `ST_IDLE;
|
||||
end
|
||||
endcase // case (state)
|
||||
end // else: !if(!rst_n_i)
|
||||
|
||||
always@*
|
||||
begin
|
||||
case (state)
|
||||
`ST_LP_MODE: begin
|
||||
pack_data <= { g_num_lanes{`DSI_SYNC_SEQ} };
|
||||
pack_size <= g_num_lanes;
|
||||
pack_valid <= pack_req_d0 && p_req_i && phy_hs_dreq_i;
|
||||
pack_flush <= ~p_req_i;
|
||||
end
|
||||
|
||||
`ST_IDLE: begin
|
||||
pack_data <= {pack_header, ecc_value};
|
||||
pack_size <= 4;
|
||||
pack_valid <= pack_req_d0;
|
||||
pack_flush <= 0;
|
||||
end
|
||||
|
||||
`ST_PAYLOAD: begin
|
||||
pack_data <= p_payload_i;
|
||||
pack_size <= g_bytes_per_clock * 3;
|
||||
pack_valid <= pack_req_d0;
|
||||
pack_flush <= 0;
|
||||
end
|
||||
|
||||
`ST_CRC: begin
|
||||
pack_data <= {crc_value[7:0], crc_value[15:8]};
|
||||
pack_size <= 2;
|
||||
pack_valid <= pack_req_d0;
|
||||
pack_flush <= ~p_req_i;
|
||||
end
|
||||
|
||||
default: begin
|
||||
pack_flush <= 0;
|
||||
pack_data <= 0;
|
||||
pack_size <= g_num_lanes;
|
||||
pack_valid <= 0;
|
||||
end
|
||||
endcase // case (state)
|
||||
end
|
||||
|
||||
assign phy_hs_request_o = p_req_i || (state != `ST_LP_MODE) || !pack_empty;
|
||||
assign phy_dvalid_o = pack_qvalid;
|
||||
assign p_dreq_o = (pack_req && p_req_i && phy_hs_dreq_i && !(state == `ST_PAYLOAD && !tx_count_next));
|
||||
|
||||
endmodule // dsi_packet_assembler
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
/*
|
||||
* DSI Core
|
||||
* Copyright (C) 2013 twl <twlostow@printf.cc>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 3.0 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library.
|
||||
*/
|
||||
|
||||
`include "dsi_defs.vh"
|
||||
|
||||
`timescale 1ns/1ns
|
||||
|
||||
/*
|
||||
* dsi_test_image_gen.v
|
||||
*
|
||||
* A simple color bar image generator.
|
||||
*/
|
||||
|
||||
module dsi_test_image_gen
|
||||
(
|
||||
input clk_i,
|
||||
input rst_n_i,
|
||||
|
||||
input fifo_full_i,
|
||||
output fifo_frame_o,
|
||||
output [23:0] fifo_pixel_o,
|
||||
output fifo_we_o,
|
||||
|
||||
input [5:0] host_a_i,
|
||||
input [31:0] host_d_i,
|
||||
output [31:0] host_d_o,
|
||||
input host_wr_i,
|
||||
|
||||
output test_enable_o
|
||||
);
|
||||
|
||||
parameter g_use_dpram = 1;
|
||||
parameter g_fb_size = 640 * 960 / 2;
|
||||
parameter g_fb_base = 32'h08000000;
|
||||
parameter g_fb_mask = 32'h0f000000;
|
||||
|
||||
reg [11:0] r_xsize;
|
||||
reg [11:0] r_ysize;
|
||||
reg r_enable;
|
||||
|
||||
reg [11:0] x, y;
|
||||
|
||||
wire fifo_we;
|
||||
reg [3:0] framebuffer [ 0:g_fb_size-1 ];
|
||||
|
||||
// synthesis translate_off
|
||||
initial begin: init_ram
|
||||
integer i;
|
||||
for(i=0;i<g_fb_size;i=i+1)
|
||||
framebuffer[i] = 0;
|
||||
end
|
||||
// synthesis translate_on
|
||||
|
||||
reg [20:0] fb_raddr, fb_waddr;
|
||||
reg [20:0] fb_raddr_next;
|
||||
reg [3:0] fb_rdata;
|
||||
reg [23:0] pixel;
|
||||
|
||||
generate
|
||||
always@(posedge clk_i)
|
||||
if(!r_enable || !rst_n_i)
|
||||
begin
|
||||
x <= 0;
|
||||
y <= 0;
|
||||
end else begin
|
||||
|
||||
if(fifo_we)
|
||||
begin
|
||||
if(x == r_xsize) begin
|
||||
x <= 0;
|
||||
if(y == r_ysize)
|
||||
y <= 0;
|
||||
else
|
||||
y <= y+1;
|
||||
end else
|
||||
x<= x + 1;
|
||||
|
||||
end
|
||||
end // else: !if(!r_enable)
|
||||
|
||||
assign fifo_we = ~fifo_full_i && r_enable;
|
||||
assign fifo_we_o = fifo_we;
|
||||
assign fifo_frame_o = (x == 0 && y == 0);
|
||||
|
||||
if(!g_use_dpram)
|
||||
begin
|
||||
assign fifo_pixel_o[23:16] = (x==0||y==0||x==r_xsize||y==r_ysize) ? 'hff : ((x & 'h30) == 'h10 ? 8'hff : 0);
|
||||
assign fifo_pixel_o[15:8] = (x & 'h30) == 'h20 ? 8'hff : 0;
|
||||
assign fifo_pixel_o[7:0] = x;
|
||||
end // if (!g_use_dpram)
|
||||
|
||||
// big framebuffer. good for testing in bigger FPGAs, but not really practical.
|
||||
if(g_use_dpram) begin
|
||||
|
||||
|
||||
|
||||
|
||||
// framebuffer DPRAM
|
||||
always@(posedge clk_i)
|
||||
begin
|
||||
if(host_a_i == `REG_DBG_DATA && host_wr_i)
|
||||
framebuffer[ host_d_i[20:0] ] <= host_d_i[27:24];
|
||||
fb_rdata <= framebuffer[fb_raddr_next];
|
||||
end
|
||||
|
||||
always @*
|
||||
if(x == r_xsize && y ==r_ysize)
|
||||
fb_raddr_next <= 0;
|
||||
else if (x == r_xsize && !y[0])
|
||||
fb_raddr_next <= fb_raddr - r_xsize;
|
||||
else if (fifo_we)
|
||||
fb_raddr_next <= fb_raddr + 1;
|
||||
else
|
||||
fb_raddr_next <= fb_raddr;
|
||||
|
||||
always@(posedge clk_i)
|
||||
if(!r_enable || !rst_n_i)
|
||||
fb_raddr <= 0;
|
||||
else
|
||||
fb_raddr <= fb_raddr_next;
|
||||
|
||||
|
||||
always@(fb_rdata)
|
||||
case(fb_rdata)
|
||||
0 : pixel <= 24'h000000;
|
||||
1 : pixel <= 24'h000080;
|
||||
2 : pixel <= 24'h0000ff;
|
||||
3 : pixel <= 24'h008000;
|
||||
4 : pixel <= 24'h008080;
|
||||
5 : pixel <= 24'h00ff00;
|
||||
6 : pixel <= 24'h00ffff;
|
||||
7 : pixel <= 24'h800000;
|
||||
8 : pixel <= 24'h800080;
|
||||
9 : pixel <= 24'h808000;
|
||||
10 : pixel <= 24'h808080;
|
||||
11 : pixel <= 24'hc0c0c0;
|
||||
12 : pixel <= 24'hff0000;
|
||||
13 : pixel <= 24'hff00ff;
|
||||
14 : pixel <= 24'hffff00;
|
||||
15 : pixel <= 24'hffffff;
|
||||
default : pixel <= 24'h000000;
|
||||
endcase // case (fb_rdata)
|
||||
|
||||
assign fifo_pixel_o = pixel;
|
||||
|
||||
|
||||
end // if (g_use_dpram)
|
||||
|
||||
|
||||
endgenerate
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge clk_i)
|
||||
if(!rst_n_i)
|
||||
begin
|
||||
r_enable <= 0;
|
||||
end else if (host_wr_i) begin
|
||||
case(host_a_i)
|
||||
`REG_TEST_CTL: r_enable <= host_d_i[0];
|
||||
`REG_TEST_XSIZE: r_xsize <= host_d_i;
|
||||
`REG_TEST_YSIZE: r_ysize <= host_d_i;
|
||||
endcase // case (host_a_i)
|
||||
end
|
||||
|
||||
assign test_enable_o = r_enable;
|
||||
|
||||
endmodule // test_image_gen
|
||||
|
|
@ -0,0 +1,237 @@
|
|||
/*
|
||||
* DSI Core
|
||||
* Copyright (C) 2013 twl <twlostow@printf.cc>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 3.0 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library.
|
||||
*/
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
`include "dsi_defs.vh"
|
||||
|
||||
/*
|
||||
* dsi_timing_gen.v
|
||||
*
|
||||
* Image timing generator - produces the display refresh timing (hsync, vsync, blanking, etc.)
|
||||
* The image is delivered by a simple FIFO interface, pixel-by-pixel. The output requests
|
||||
* particular packets from the Packet Assembler.
|
||||
*/
|
||||
|
||||
module dsi_timing_gen
|
||||
(
|
||||
clk_i,
|
||||
rst_n_i,
|
||||
|
||||
fifo_empty_i,
|
||||
fifo_rd_o,
|
||||
fifo_pixels_i,
|
||||
fifo_frame_i,
|
||||
fifo_got_frame_i,
|
||||
p_req_o,
|
||||
p_islong_o,
|
||||
p_type_o,
|
||||
p_wcount_o,
|
||||
p_command_o,
|
||||
p_payload_o,
|
||||
p_dreq_i,
|
||||
p_last_o,
|
||||
|
||||
host_a_i,
|
||||
host_d_i,
|
||||
host_d_o,
|
||||
host_wr_i
|
||||
);
|
||||
|
||||
parameter g_pixels_per_clock = 1;
|
||||
|
||||
localparam g_pixel_width = g_pixels_per_clock * 24;
|
||||
|
||||
input clk_i;
|
||||
input rst_n_i;
|
||||
|
||||
input fifo_empty_i;
|
||||
input fifo_got_frame_i;
|
||||
|
||||
output fifo_rd_o;
|
||||
input [g_pixel_width - 1: 0] fifo_pixels_i;
|
||||
input fifo_frame_i;
|
||||
|
||||
output reg p_req_o, p_islong_o;
|
||||
output reg [5:0] p_type_o;
|
||||
output reg [15:0] p_wcount_o, p_command_o;
|
||||
output [g_pixel_width-1:0] p_payload_o;
|
||||
|
||||
input p_dreq_i;
|
||||
|
||||
output reg p_last_o;
|
||||
|
||||
input [3:0] host_a_i;
|
||||
input [31:0] host_d_i;
|
||||
output reg [31:0] host_d_o;
|
||||
input host_wr_i;
|
||||
|
||||
|
||||
`define ST_BPORCH 0
|
||||
`define ST_FPORCH 1
|
||||
`define ST_HSYNC_START 2
|
||||
`define ST_HSYNC_END 3
|
||||
`define ST_HSYNC_ACTIVE 4
|
||||
`define ST_LINE 6
|
||||
`define ST_VSYNC_PACKET 7
|
||||
`define ST_STOP 8
|
||||
`define ST_LONG_PACKET 9
|
||||
`define ST_LP 10
|
||||
|
||||
|
||||
|
||||
|
||||
reg [3:0] state, next_state;
|
||||
|
||||
reg [11:0] h_count, v_count;
|
||||
|
||||
reg [11:0] h_front_porch, h_back_porch, h_active, h_total;
|
||||
reg [11:0] v_front_porch, v_back_porch, v_active, v_total;
|
||||
|
||||
reg enable = 0;
|
||||
reg disp_en_mask;
|
||||
|
||||
reg [11:0] pixel_counter;
|
||||
|
||||
|
||||
// host registers
|
||||
always@(posedge clk_i)
|
||||
if(!rst_n_i)
|
||||
begin
|
||||
enable <= 0;
|
||||
end else if(host_wr_i) begin
|
||||
case (host_a_i)
|
||||
0:h_front_porch <= host_d_i;
|
||||
1:h_back_porch <= host_d_i;
|
||||
2:h_active <= host_d_i;
|
||||
3:h_total <= host_d_i;
|
||||
4:v_front_porch <= host_d_i;
|
||||
5:v_back_porch <= host_d_i;
|
||||
6:v_active <= host_d_i;
|
||||
7:v_total <= host_d_i;
|
||||
8:enable<=host_d_i[0];
|
||||
endcase // case (host_a_i)
|
||||
end
|
||||
|
||||
task send(input long, input [5:0] ptype, input [15:0] count, input[3:0] _next_state, input is_last);
|
||||
begin
|
||||
if(p_dreq_i) begin
|
||||
p_islong_o <= long;
|
||||
p_type_o <= ptype;
|
||||
p_wcount_o <= count;
|
||||
p_command_o <= 0;
|
||||
p_last_o <= is_last;
|
||||
|
||||
pixel_counter <= count;
|
||||
if(long)
|
||||
state <= `ST_LONG_PACKET;
|
||||
else
|
||||
state <= _next_state;
|
||||
|
||||
next_state <= _next_state;
|
||||
end // if (p_dreq_i)
|
||||
end
|
||||
endtask // send
|
||||
|
||||
reg push_pixels, push_pixels_d0;
|
||||
|
||||
always@(posedge clk_i)
|
||||
if(!rst_n_i || !enable) begin
|
||||
v_count <= 0;
|
||||
state <= `ST_LP;
|
||||
pixel_counter <= h_total;
|
||||
p_req_o <= 0;
|
||||
p_last_o <= 0;
|
||||
|
||||
disp_en_mask <= 0;
|
||||
push_pixels <= 0;
|
||||
push_pixels_d0 <= 0;
|
||||
end else begin
|
||||
push_pixels_d0 <= push_pixels;
|
||||
|
||||
case (state)
|
||||
`ST_FPORCH:
|
||||
begin
|
||||
push_pixels<=0;
|
||||
push_pixels_d0<=0;
|
||||
|
||||
if(v_count == v_back_porch) begin
|
||||
disp_en_mask <= 1;
|
||||
end else if(v_count == v_front_porch) begin
|
||||
disp_en_mask <= 0;
|
||||
end
|
||||
|
||||
send(1, `PTYPE_BLANKING, h_front_porch, `ST_HSYNC_START, 0);
|
||||
end // case: `ST_FPORCH
|
||||
|
||||
`ST_HSYNC_START: begin
|
||||
p_req_o <= 1;
|
||||
|
||||
if(v_count == 0)
|
||||
send(0, `PTYPE_VSYNC_START, h_total, `ST_BPORCH, 0);
|
||||
else if (v_count == v_total)
|
||||
send(0, `PTYPE_HSYNC_START, h_total, `ST_LP, 1);
|
||||
else
|
||||
send(0, `PTYPE_HSYNC_START, h_total, `ST_BPORCH, 0);
|
||||
end
|
||||
|
||||
`ST_BPORCH:
|
||||
send(1, `PTYPE_BLANKING, h_back_porch, `ST_LINE, 0);
|
||||
|
||||
`ST_LINE:
|
||||
begin
|
||||
send(1, disp_en_mask ? `PTYPE_RGB24: `PTYPE_BLANKING, h_active, `ST_FPORCH, 0);
|
||||
if(p_dreq_i) begin
|
||||
if(v_count == v_total)
|
||||
v_count <= 0;
|
||||
else
|
||||
v_count <= v_count + 1;
|
||||
push_pixels <= disp_en_mask;
|
||||
end
|
||||
end
|
||||
|
||||
`ST_LP: begin
|
||||
p_req_o <= 0;
|
||||
if(pixel_counter == 0) begin
|
||||
if(!fifo_empty_i) begin
|
||||
state <= `ST_HSYNC_START;
|
||||
v_count <= 0;
|
||||
end
|
||||
end else
|
||||
pixel_counter <= pixel_counter - 1;
|
||||
end
|
||||
|
||||
`ST_LONG_PACKET:
|
||||
begin
|
||||
if(p_dreq_i)
|
||||
pixel_counter <= pixel_counter - 3;
|
||||
if(pixel_counter == 3)
|
||||
begin
|
||||
push_pixels <=0;
|
||||
state <= next_state;
|
||||
end
|
||||
end
|
||||
|
||||
endcase // case (state)
|
||||
end // else: !if(!rst_n_i || !enable)
|
||||
|
||||
assign fifo_rd_o = (push_pixels && p_dreq_i);
|
||||
assign p_payload_o = (push_pixels || push_pixels_d0 ? fifo_pixels_i : 0);
|
||||
|
||||
endmodule // dsi_timing_gen
|
||||
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* DSI Core
|
||||
* Copyright (C) 2013 twl <twlostow@printf.cc>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 3.0 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library.
|
||||
*/
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
/*
|
||||
* dsi_utils.v
|
||||
*
|
||||
* Some utility stuff (parity/CRC generators)
|
||||
*/
|
||||
|
||||
module dsi_parity
|
||||
(
|
||||
input [23:0] d_i,
|
||||
output [7:0] p_o
|
||||
);
|
||||
|
||||
assign p_o[0]=^{d_i[2:0], d_i[5:4], d_i[7], d_i[11:10], d_i[13], d_i[16], d_i[23:20]};
|
||||
assign p_o[1]=^{d_i[1:0], d_i[4:3], d_i[6], d_i[8], d_i[10], d_i[12], d_i[14], d_i[17], d_i[23:20]};
|
||||
assign p_o[2]=^{d_i[0], d_i[3:2], d_i[6:5], d_i[9], d_i[12:11], d_i[15], d_i[18], d_i[22:20] };
|
||||
assign p_o[3]=^{d_i[3:1], d_i[9:7], d_i[15:13], d_i[21:19], d_i[23]};
|
||||
assign p_o[4]=^{d_i[9:4], d_i[20:16], d_i[23:22]};
|
||||
assign p_o[5]=^{d_i[19:10], d_i[23:21]};
|
||||
assign p_o[7:6]=2'b0;
|
||||
endmodule // dsi_parity
|
||||
|
||||
module dsi_crc_comb (input[15:0] crc, input[7:0] x, output [15:0] crc_new);
|
||||
assign crc_new[0] = crc[8] ^ crc[12] ^ x[7-0] ^ x[7-4];
|
||||
assign crc_new[1] = crc[9] ^ crc[13] ^ x[7-1] ^ x[7-5];
|
||||
assign crc_new[2] = crc[10] ^ crc[14] ^ x[7-2] ^ x[7-6];
|
||||
assign crc_new[3] = crc[11] ^ crc[15] ^ x[7-3] ^ x[7-7];
|
||||
assign crc_new[4] = crc[12] ^ x[7-4];
|
||||
assign crc_new[5] = crc[8] ^ crc[12] ^ crc[13] ^ x[7-0] ^ x[7-4] ^ x[7-5];
|
||||
assign crc_new[6] = crc[9] ^ crc[13] ^ crc[14] ^ x[7-1] ^ x[7-5] ^ x[7-6];
|
||||
assign crc_new[7] = crc[10] ^ crc[14] ^ crc[15] ^ x[7-2] ^ x[7-6] ^ x[7-7];
|
||||
assign crc_new[8] = crc[0] ^ crc[11] ^ crc[15] ^ x[7-3] ^ x[7-7];
|
||||
assign crc_new[9] = crc[1] ^ crc[12] ^ x[7-4];
|
||||
assign crc_new[10] = crc[2] ^ crc[13] ^ x[7-5];
|
||||
assign crc_new[11] = crc[3] ^ crc[14] ^ x[7-6];
|
||||
assign crc_new[12] = crc[4] ^ crc[8] ^ crc[12] ^ crc[15] ^ x[7-0] ^ x[7-4] ^ x[7-7];
|
||||
assign crc_new[13] = crc[5] ^ crc[9] ^ crc[13] ^ x[7-1] ^ x[7-5];
|
||||
assign crc_new[14] = crc[6] ^ crc[10] ^ crc[14] ^ x[7-2] ^ x[7-6];
|
||||
assign crc_new[15] = crc[7] ^ crc[11] ^ crc[15] ^ x[7-3] ^ x[7-7];
|
||||
endmodule // dsi_crc_comb
|
||||
|
||||
|
||||
module dsi_crc
|
||||
(
|
||||
clk_i,
|
||||
rst_i,
|
||||
valid_i,
|
||||
nbytes_i,
|
||||
d_i,
|
||||
crc_o);
|
||||
|
||||
parameter g_max_data_bytes = 3;
|
||||
|
||||
input [g_max_data_bytes*8-1:0] d_i;
|
||||
input valid_i;
|
||||
input [2:0] nbytes_i;
|
||||
input clk_i;
|
||||
input rst_i;
|
||||
output [15:0] crc_o;
|
||||
|
||||
reg [15:0] crc_cur;
|
||||
|
||||
wire [15:0] stages_in [0:g_max_data_bytes-1];
|
||||
wire [15:0] stages_out [0:g_max_data_bytes-1];
|
||||
|
||||
generate
|
||||
genvar i ;
|
||||
for(i=0;i<g_max_data_bytes;i=i+1)
|
||||
begin
|
||||
if(i != g_max_data_bytes-1)
|
||||
assign stages_in[i] = (nbytes_i == (i+1) ? crc_cur : stages_out[i+1]);
|
||||
dsi_crc_comb stageX(stages_in[i], d_i[8*i+7:8*i], stages_out[i]);
|
||||
end
|
||||
|
||||
assign stages_in[g_max_data_bytes-1] = crc_cur;
|
||||
endgenerate
|
||||
|
||||
always@(posedge clk_i)
|
||||
if(rst_i)
|
||||
crc_cur <= 16'hffff;
|
||||
else if(valid_i)
|
||||
crc_cur <= stages_out[0];
|
||||
|
||||
assign crc_o = {crc_cur[0], crc_cur[1],crc_cur[2], crc_cur[3],
|
||||
crc_cur[4], crc_cur[5],crc_cur[6], crc_cur[7],
|
||||
crc_cur[8], crc_cur[9],crc_cur[10], crc_cur[11],
|
||||
crc_cur[12], crc_cur[13],crc_cur[14], crc_cur[15]};
|
||||
|
||||
|
||||
endmodule // dsi_crc
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
target = "xilinx"
|
||||
action = "synthesis"
|
||||
|
||||
fetchto = "../../ip_cores"
|
||||
|
||||
syn_device = "xc6slx45t"
|
||||
syn_grade = "-3"
|
||||
syn_package = "fgg484"
|
||||
syn_top = "spec_top"
|
||||
syn_project = "dsi_test.xise"
|
||||
|
||||
modules = { "local" : [ "../../top/spec" ] }
|
||||
|
||||
files = "boot.ram"
|
||||
|
|
@ -0,0 +1 @@
|
|||
../../../software/bootloader/boot.ram
|
||||
|
|
@ -0,0 +1,693 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_top" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_top" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="-g INIT_9K:Yes" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="spec_top" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_top_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="spec_top_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_top_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_top_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="dsi_test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-06-07T20:05:36" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="364373CDC30042E810BDAF8C3E4A9A80" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="../../top/spec/spec_top.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../top/spec/dsi_pll_spartan6.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/dsi_core/dphy_lane.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/dsi_core/dphy_serdes.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/dsi_core/dsi_core.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/dsi_core/dsi_fifo.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/dsi_core/dsi_packer.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/dsi_core/dsi_packet_assembler.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/dsi_core/dsi_test_image_gen.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/dsi_core/dsi_timing_gen.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/dsi_core/dsi_utils.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../top/spec/spec_reset_gen.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
|
||||
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|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../../../wr-repos/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
|
||||
|
||||
</project>
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
files = ["spec_top.vhd", "spec_top.ucf", "spec_reset_gen.vhd", "dsi_pll_spartan6.v"]
|
||||
|
||||
fetchto = "../../ip_cores"
|
||||
|
||||
modules = {
|
||||
"local" : ["../../rtl/dsi_core" ],
|
||||
"git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git" ]
|
||||
}
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
// file: dsi_pll_spartan6.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1___255.000______0.000______50.0______200.079____379.637
|
||||
// CLK_OUT2____31.875______0.000______50.0______272.567____379.637
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________20____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "dsi_pll_spartan6,clk_wiz_v3_2,{component_name=dsi_pll_spartan6,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=50.000,clkin2_period=50.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
|
||||
module dsi_pll_spartan6
|
||||
(// Clock in ports
|
||||
input clk_in_i,
|
||||
// Clock out ports
|
||||
output clk_phy_o,
|
||||
output clk_sys_o,
|
||||
// Status and control signals
|
||||
output locked_o
|
||||
);
|
||||
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
IBUFG clkin1_buf
|
||||
(.O (clkin1),
|
||||
.I (clk_in_i));
|
||||
|
||||
|
||||
// Clocking primitive
|
||||
//------------------------------------
|
||||
// Instantiation of the PLL primitive
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire clkfbout;
|
||||
wire clkout2_unused;
|
||||
wire clkout3_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
|
||||
PLL_BASE
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLK_FEEDBACK ("CLKFBOUT"),
|
||||
.COMPENSATION ("INTERNAL"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT (51),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKOUT0_DIVIDE (4),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT1_DIVIDE (32),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.CLKIN_PERIOD (50.000),
|
||||
.REF_JITTER (0.010))
|
||||
pll_base_inst
|
||||
// Output clocks
|
||||
(.CLKFBOUT (clkfbout),
|
||||
.CLKOUT0 (clkout0),
|
||||
.CLKOUT1 (clkout1),
|
||||
.CLKOUT2 (clkout2_unused),
|
||||
.CLKOUT3 (clkout3_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
// Status and control signals
|
||||
.LOCKED (locked_o),
|
||||
.RST (1'b0),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout),
|
||||
.CLKIN (clkin1));
|
||||
|
||||
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
assign clk_phy_o = clkout0;
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (clk_sys_o),
|
||||
.I (clkout1));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
library ieee;
|
||||
use ieee.STD_LOGIC_1164.all;
|
||||
use ieee.NUMERIC_STD.all;
|
||||
|
||||
use work.gencores_pkg.all;
|
||||
|
||||
entity spec_reset_gen is
|
||||
|
||||
port (
|
||||
clk_sys_i : in std_logic;
|
||||
|
||||
rst_pcie_n_a_i : in std_logic;
|
||||
rst_button_n_a_i : in std_logic;
|
||||
|
||||
rst_n_o : out std_logic
|
||||
);
|
||||
|
||||
end spec_reset_gen;
|
||||
|
||||
architecture behavioral of spec_reset_gen is
|
||||
|
||||
signal powerup_cnt : unsigned(7 downto 0) := x"00";
|
||||
signal button_synced_n : std_logic;
|
||||
signal pcie_synced_n : std_logic;
|
||||
signal powerup_n : std_logic := '0';
|
||||
|
||||
begin -- behavioral
|
||||
|
||||
U_EdgeDet_PCIe : gc_sync_ffs port map (
|
||||
clk_i => clk_sys_i,
|
||||
rst_n_i => '1',
|
||||
data_i => rst_pcie_n_a_i,
|
||||
ppulse_o => pcie_synced_n);
|
||||
|
||||
U_Sync_Button : gc_sync_ffs port map (
|
||||
clk_i => clk_sys_i,
|
||||
rst_n_i => '1',
|
||||
data_i => rst_button_n_a_i,
|
||||
synced_o => button_synced_n);
|
||||
|
||||
p_powerup_reset : process(clk_sys_i)
|
||||
begin
|
||||
if rising_edge(clk_sys_i) then
|
||||
if(powerup_cnt /= x"ff") then
|
||||
powerup_cnt <= powerup_cnt + 1;
|
||||
powerup_n <= '0';
|
||||
else
|
||||
powerup_n <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
|
||||
|
||||
end behavioral;
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
NET "CLK_20M_I" LOC = H12;
|
||||
NET "CLK_20M_I" IOSTANDARD = "LVCMOS25";
|
||||
|
||||
NET "uart_rxd_i" LOC= A2;
|
||||
NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
|
||||
|
||||
NET "uart_txd_o" LOC= B2;
|
||||
NET "uart_txd_o" IOSTANDARD=LVCMOS25;
|
||||
|
||||
NET "button1_n_i" LOC = C22;
|
||||
NET "button1_n_i" IOSTANDARD = "LVCMOS18";
|
||||
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2013/06/07
|
||||
NET "clk_20m_i" TNM_NET = clk_20m_i;
|
||||
TIMESPEC TS_clk_20m_i = PERIOD "clk_20m_i" 20 MHz HIGH 50 %;
|
||||
|
||||
NET "dsi_clk_p_o" LOC = V11;
|
||||
#15_p
|
||||
NET "dsi_clk_n_o" LOC = W11;
|
||||
#15_n
|
||||
NET "dsi_hs_p_o[0]" LOC = Y16;
|
||||
#30_p
|
||||
NET "dsi_hs_n_o[0]" LOC = W15;
|
||||
#30_n
|
||||
NET "dsi_hs_p_o[1]" LOC = V13;
|
||||
#24_p
|
||||
NET "dsi_hs_n_o[1]" LOC = W13;
|
||||
#24_n
|
||||
NET "dsi_hs_p_o[2]" LOC = U9;
|
||||
#07p
|
||||
NET "dsi_hs_n_o[2]" LOC = V9;
|
||||
#07n
|
||||
|
||||
#NET "dsi_hs_p_o[3]" LOC = V17;
|
||||
#07p
|
||||
#NET "dsi_hs_n_o[3]" LOC = W18;
|
||||
#07n
|
||||
|
||||
NET "dsi_lp_p_o[0]" LOC = Y14;
|
||||
#28_n
|
||||
NET "dsi_lp_p_o[0]" IOSTANDARD="LVCMOS25";
|
||||
|
||||
NET "dsi_lp_n_o[0]" LOC = V17;
|
||||
#32_p
|
||||
NET "dsi_lp_n_o[0]" IOSTANDARD="LVCMOS25";
|
||||
|
||||
NET "dsi_lp_p_o[1]" LOC = AB15;
|
||||
#21_n
|
||||
NET "dsi_lp_p_o[1]" IOSTANDARD="LVCMOS25";
|
||||
|
||||
NET "dsi_lp_n_o[1]" LOC = W14;
|
||||
#28_p
|
||||
NET "dsi_lp_n_o[1]" IOSTANDARD="LVCMOS25";
|
||||
|
||||
NET "dsi_lp_p_o[2]" LOC = T8;
|
||||
#4_n
|
||||
NET "dsi_lp_p_o[2]" IOSTANDARD="LVCMOS25";
|
||||
|
||||
NET "dsi_lp_n_o[2]" LOC = W10;
|
||||
#11_p
|
||||
NET "dsi_lp_n_o[2]" IOSTANDARD="LVCMOS25";
|
||||
|
||||
#NET "dsi_lp_p_o[3]" LOC = A20;
|
||||
#4_n
|
||||
#NET "dsi_lp_p_o[3]" IOSTANDARD="LVCMOS25";
|
||||
|
||||
#NET "dsi_lp_n_o[3]" LOC = AA18;
|
||||
#11_p
|
||||
#NET "dsi_lp_n_o[3]" IOSTANDARD="LVCMOS25";
|
||||
|
||||
|
||||
NET "dsi_clk_lp_p_o" LOC = Y10;
|
||||
#11_n
|
||||
NET "dsi_clk_lp_p_o" IOSTANDARD="LVCMOS25";
|
||||
|
||||
NET "dsi_clk_lp_n_o" LOC = Y15;
|
||||
#19_p
|
||||
NET "dsi_clk_lp_n_o" IOSTANDARD="LVCMOS25";
|
||||
|
||||
NET "dsi_resetb_o" LOC = F16;
|
||||
#04_p
|
||||
NET "dsi_resetb_o" IOSTANDARD="LVCMOS25";
|
||||
|
||||
|
||||
NET "dsi_hifa_o" LOC = E16;
|
||||
#02_n
|
||||
NET "dsi_hifa_o" IOSTANDARD="LVCMOS25";
|
||||
|
||||
NET "dsi_pifa_o" LOC = W6;
|
||||
#02_p
|
||||
NET "dsi_pifa_o" IOSTANDARD="LVCMOS25";
|
||||
|
|
@ -0,0 +1,259 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
use work.wishbone_pkg.all;
|
||||
|
||||
entity spec_top is
|
||||
|
||||
port (
|
||||
clk_20m_i : in std_logic;
|
||||
|
||||
button1_n_i : in std_logic := 'H';
|
||||
|
||||
uart_txd_o : out std_logic;
|
||||
uart_rxd_i : in std_logic;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
-- DSI ports
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
dsi_clk_p_o : out std_logic;
|
||||
dsi_clk_n_o : out std_logic;
|
||||
|
||||
dsi_clk_lp_p_o : out std_logic;
|
||||
dsi_clk_lp_n_o : out std_logic;
|
||||
|
||||
dsi_hs_p_o : out std_logic_vector(2 downto 0);
|
||||
dsi_hs_n_o : out std_logic_vector(2 downto 0);
|
||||
|
||||
dsi_lp_p_o : out std_logic_vector(2 downto 0);
|
||||
dsi_lp_n_o : out std_logic_vector(2 downto 0);
|
||||
|
||||
dsi_resetb_o : out std_logic;
|
||||
dsi_hifa_o : out std_logic;
|
||||
dsi_pifa_o : out std_logic
|
||||
);
|
||||
|
||||
end spec_top;
|
||||
|
||||
architecture rtl of spec_top is
|
||||
|
||||
component dsi_core is
|
||||
generic(
|
||||
g_pixels_per_clock : integer := 1;
|
||||
g_lanes : integer := 3;
|
||||
g_fifo_size : integer := 1024;
|
||||
g_invert_lanes : integer := 7;
|
||||
g_invert_clock : integer := 1);
|
||||
port(
|
||||
clk_sys_i : in std_logic;
|
||||
clk_phy_i : in std_logic;
|
||||
|
||||
rst_n_i : in std_logic;
|
||||
|
||||
pll_locked_i : in std_logic;
|
||||
|
||||
frame_ready_o : out std_logic;
|
||||
|
||||
fifo_full_o : out std_logic;
|
||||
fifo_pixels_i : in std_logic_vector (24 * g_pixels_per_clock-1 downto 0) := (others => '0');
|
||||
fifo_frame_i : in std_logic;
|
||||
fifo_wr_i : in std_logic;
|
||||
|
||||
dsi_clk_p_o : out std_logic;
|
||||
dsi_clk_n_o : out std_logic;
|
||||
dsi_clk_lp_p_o : out std_logic;
|
||||
dsi_clk_lp_n_o : out std_logic;
|
||||
dsi_clk_lp_oe_o : out std_logic;
|
||||
|
||||
dsi_hs_p_o : out std_logic_vector(g_lanes-1 downto 0);
|
||||
dsi_hs_n_o : out std_logic_vector(g_lanes-1 downto 0);
|
||||
|
||||
dsi_lp_p_o : out std_logic_vector(g_lanes-1 downto 0);
|
||||
dsi_lp_n_o : out std_logic_vector(g_lanes-1 downto 0);
|
||||
|
||||
|
||||
dsi_lp_oe_o : out std_logic_vector(g_lanes-1 downto 0);
|
||||
|
||||
dsi_reset_n_o : out std_logic;
|
||||
|
||||
host_a_i : in std_logic_vector(5 downto 0);
|
||||
host_d_i : in std_logic_vector(31 downto 0);
|
||||
host_d_o : out std_logic_vector(31 downto 0);
|
||||
host_wr_i : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component dsi_pll_spartan6
|
||||
port (
|
||||
clk_in_i : in std_logic;
|
||||
clk_sys_o : out std_logic;
|
||||
clk_phy_o : out std_logic;
|
||||
locked_o : out std_logic);
|
||||
end component;
|
||||
|
||||
component spec_reset_gen
|
||||
port (
|
||||
clk_sys_i : in std_logic;
|
||||
rst_pcie_n_a_i : in std_logic;
|
||||
rst_button_n_a_i : in std_logic;
|
||||
rst_n_o : out std_logic);
|
||||
end component;
|
||||
|
||||
constant c_cnx_slave_ports : integer := 1;
|
||||
constant c_cnx_master_ports : integer := 3;
|
||||
|
||||
constant c_master_cpu_i : integer := 0;
|
||||
|
||||
constant c_slave_dpram : integer := 0;
|
||||
constant c_slave_uart : integer := 1;
|
||||
constant c_slave_dsi : integer := 2;
|
||||
|
||||
signal cnx_slave_in : t_wishbone_slave_in_array(c_cnx_slave_ports-1 downto 0);
|
||||
signal cnx_slave_out : t_wishbone_slave_out_array(c_cnx_slave_ports-1 downto 0);
|
||||
|
||||
signal cnx_master_in : t_wishbone_master_in_array(c_cnx_master_ports-1 downto 0);
|
||||
signal cnx_master_out : t_wishbone_master_out_array(c_cnx_master_ports-1 downto 0);
|
||||
|
||||
constant c_cfg_base_addr : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
|
||||
(0 => x"00000000", -- 64KB of fpga memory
|
||||
1 => x"00010000", -- The second port to the same memory
|
||||
2 => x"00020000"); -- Peripherals
|
||||
|
||||
constant c_cfg_base_mask : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
|
||||
(0 => x"000f0000",
|
||||
1 => x"000f0000",
|
||||
2 => x"000f0000");
|
||||
|
||||
signal cpu_iwb_out : t_wishbone_master_out;
|
||||
signal cpu_iwb_in : t_wishbone_master_in;
|
||||
|
||||
signal rst_n, clk_phy, clk_sys, pll_locked, pll_locked_n, dsi_wr : std_logic;
|
||||
signal dsi_lp_p_int, dsi_lp_n_int, dsi_lp_oe : std_logic_vector(2 downto 0);
|
||||
signal dsi_clk_lp_p, dsi_clk_lp_n, dsi_clk_lp_oe : std_logic;
|
||||
|
||||
begin -- rtl
|
||||
|
||||
U_PLL : dsi_pll_spartan6
|
||||
port map (
|
||||
clk_in_i => clk_20m_i,
|
||||
clk_sys_o => clk_sys,
|
||||
clk_phy_o => clk_phy,
|
||||
locked_o => pll_locked);
|
||||
|
||||
pll_locked_n <= not pll_locked;
|
||||
|
||||
U_Reset_Gen : spec_reset_gen
|
||||
port map (
|
||||
clk_sys_i => clk_sys,
|
||||
rst_pcie_n_a_i => pll_locked_n,
|
||||
rst_button_n_a_i => button1_n_i,
|
||||
rst_n_o => rst_n);
|
||||
|
||||
U_CPU : xwb_lm32
|
||||
generic map (
|
||||
g_profile => "medium")
|
||||
port map (
|
||||
clk_sys_i => clk_sys,
|
||||
rst_n_i => rst_n,
|
||||
irq_i => x"00000000",
|
||||
dwb_o => cnx_slave_in(0),
|
||||
dwb_i => cnx_slave_out(0),
|
||||
iwb_o => cpu_iwb_out,
|
||||
iwb_i => cpu_iwb_in);
|
||||
|
||||
U_Intercon : xwb_crossbar
|
||||
generic map (
|
||||
g_num_masters => c_cnx_slave_ports,
|
||||
g_num_slaves => c_cnx_master_ports,
|
||||
g_registered => true,
|
||||
g_address => c_cfg_base_addr,
|
||||
g_mask => c_cfg_base_mask)
|
||||
port map (
|
||||
clk_sys_i => clk_sys,
|
||||
rst_n_i => rst_n,
|
||||
slave_i => cnx_slave_in,
|
||||
slave_o => cnx_slave_out,
|
||||
master_i => cnx_master_in,
|
||||
master_o => cnx_master_out);
|
||||
|
||||
U_DPRAM : xwb_dpram
|
||||
generic map (
|
||||
g_size => 16384, -- 16kB
|
||||
g_init_file => "boot.ram",
|
||||
g_must_have_init_file => true,
|
||||
g_slave1_interface_mode => PIPELINED,
|
||||
g_slave2_interface_mode => PIPELINED,
|
||||
g_slave1_granularity => BYTE,
|
||||
g_slave2_granularity => BYTE)
|
||||
port map (
|
||||
clk_sys_i => clk_sys,
|
||||
rst_n_i => rst_n,
|
||||
slave1_i => cnx_master_out(c_slave_dpram),
|
||||
slave1_o => cnx_master_in(c_slave_dpram),
|
||||
slave2_i => cpu_iwb_out,
|
||||
slave2_o => cpu_iwb_in);
|
||||
|
||||
U_UART : xwb_simple_uart
|
||||
generic map (
|
||||
g_interface_mode => PIPELINED,
|
||||
g_address_granularity => BYTE)
|
||||
port map (
|
||||
clk_sys_i => clk_sys,
|
||||
rst_n_i => rst_n,
|
||||
slave_i => cnx_master_out(c_slave_uart),
|
||||
slave_o => cnx_master_in(c_slave_uart),
|
||||
uart_rxd_i => uart_rxd_i,
|
||||
uart_txd_o => uart_txd_o);
|
||||
|
||||
|
||||
U_DSI_Core : dsi_core
|
||||
port map (
|
||||
clk_sys_i => clk_sys,
|
||||
clk_phy_i => clk_phy,
|
||||
rst_n_i => rst_n,
|
||||
pll_locked_i => pll_locked,
|
||||
-- frame_ready_o => frame_ready_o,
|
||||
fifo_full_o => open,
|
||||
-- fifo_pixels_i => x"000000000000",
|
||||
fifo_frame_i => '0',
|
||||
fifo_wr_i => '0',
|
||||
dsi_clk_p_o => dsi_clk_p_o,
|
||||
dsi_clk_n_o => dsi_clk_n_o,
|
||||
dsi_clk_lp_n_o => dsi_clk_lp_n,
|
||||
dsi_clk_lp_p_o => dsi_clk_lp_p,
|
||||
dsi_clk_lp_oe_o => dsi_clk_lp_oe,
|
||||
dsi_hs_p_o => dsi_hs_p_o,
|
||||
dsi_hs_n_o => dsi_hs_n_o,
|
||||
dsi_lp_p_o => dsi_lp_p_int,
|
||||
dsi_lp_n_o => dsi_lp_n_int,
|
||||
dsi_lp_oe_o => dsi_lp_oe,
|
||||
dsi_reset_n_o => dsi_resetb_o,
|
||||
host_a_i => cnx_master_out(c_slave_dsi).adr(7 downto 2),
|
||||
host_d_i => cnx_master_out(c_slave_dsi).dat,
|
||||
host_d_o => cnx_master_in(c_slave_dsi).dat,
|
||||
host_wr_i => dsi_wr);
|
||||
|
||||
dsi_wr <= cnx_master_out(c_slave_dsi).stb and cnx_master_out(c_slave_dsi).cyc and cnx_master_out(c_slave_dsi).we;
|
||||
|
||||
gen_lp_tristates : for i in 0 to 2 generate
|
||||
dsi_lp_p_o(i) <= not dsi_lp_p_int(i) when dsi_lp_oe(i) = '1' else '1';
|
||||
dsi_lp_n_o(i) <= not dsi_lp_n_int(i) when dsi_lp_oe(i) = '1' else '1';
|
||||
end generate gen_lp_tristates;
|
||||
|
||||
dsi_clk_lp_p_o <= not dsi_clk_lp_p when dsi_clk_lp_oe = '1' else '1';
|
||||
dsi_clk_lp_n_o <= not dsi_clk_lp_n when dsi_clk_lp_oe = '1' else '1';
|
||||
|
||||
process(clk_sys)
|
||||
begin
|
||||
if rising_edge(clk_sys) then
|
||||
cnx_master_in(c_slave_dsi).ack <= cnx_master_out(c_slave_dsi).stb and cnx_master_out(c_slave_dsi).cyc;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cnx_master_in(c_slave_dsi).stall <= '0';
|
||||
cnx_master_in(c_slave_dsi).err <= '0';
|
||||
|
||||
dsi_pifa_o <= '0';
|
||||
dsi_hifa_o <= '0';
|
||||
end rtl;
|
||||
Loading…
Reference in New Issue