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2013-12-22 15:36:11 +01:00
hdl initial commit 2013-12-22 15:36:11 +01:00
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README initial commit 2013-12-22 15:36:11 +01:00

DSI Core Readme
------------------------

0. Disclaimer

This project implements a MIPI DSI (MIPI Display Serial Interface) Verilog core.
Since the DSI specification is non-public and requires an NDA, the core is based on
using bits and pieces available throughout the Web: presentations, display controller/SOC
datasheets, various application notes and Android kernel drivers. The author is not 
associated in any way with the MIPI Alliance. The core is provided as-is, it has never been
verified for compliance with the DSI standard and it probably lacks many of its features.
To sum up: you use it at your own risk, there's no warranty.