186 lines
4.9 KiB
Verilog
186 lines
4.9 KiB
Verilog
/*
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* DSI Core
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* Copyright (C) 2013 twl <twlostow@printf.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 3.0 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library.
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*/
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`include "dsi_defs.vh"
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`timescale 1ns/1ns
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/*
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* dsi_test_image_gen.v
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*
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* A simple color bar image generator.
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*/
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module dsi_test_image_gen
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(
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input clk_i,
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input rst_n_i,
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input fifo_full_i,
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output fifo_frame_o,
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output [23:0] fifo_pixel_o,
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output fifo_we_o,
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input [5:0] host_a_i,
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input [31:0] host_d_i,
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output [31:0] host_d_o,
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input host_wr_i,
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output test_enable_o
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);
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parameter g_use_dpram = 1;
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parameter g_fb_size = 640 * 960 / 2;
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parameter g_fb_base = 32'h08000000;
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parameter g_fb_mask = 32'h0f000000;
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reg [11:0] r_xsize;
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reg [11:0] r_ysize;
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reg r_enable;
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reg [11:0] x, y;
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wire fifo_we;
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reg [3:0] framebuffer [ 0:g_fb_size-1 ];
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// synthesis translate_off
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initial begin: init_ram
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integer i;
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for(i=0;i<g_fb_size;i=i+1)
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framebuffer[i] = 0;
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end
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// synthesis translate_on
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reg [20:0] fb_raddr, fb_waddr;
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reg [20:0] fb_raddr_next;
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reg [3:0] fb_rdata;
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reg [23:0] pixel;
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generate
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always@(posedge clk_i)
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if(!r_enable || !rst_n_i)
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begin
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x <= 0;
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y <= 0;
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end else begin
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if(fifo_we)
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begin
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if(x == r_xsize) begin
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x <= 0;
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if(y == r_ysize)
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y <= 0;
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else
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y <= y+1;
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end else
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x<= x + 1;
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end
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end // else: !if(!r_enable)
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assign fifo_we = ~fifo_full_i && r_enable;
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assign fifo_we_o = fifo_we;
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assign fifo_frame_o = (x == 0 && y == 0);
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if(!g_use_dpram)
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begin
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assign fifo_pixel_o[23:16] = (x==0||y==0||x==r_xsize||y==r_ysize) ? 'hff : ((x & 'h30) == 'h10 ? 8'hff : 0);
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assign fifo_pixel_o[15:8] = (x & 'h30) == 'h20 ? 8'hff : 0;
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assign fifo_pixel_o[7:0] = x;
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end // if (!g_use_dpram)
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// big framebuffer. good for testing in bigger FPGAs, but not really practical.
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if(g_use_dpram) begin
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// framebuffer DPRAM
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always@(posedge clk_i)
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begin
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if(host_a_i == `REG_DBG_DATA && host_wr_i)
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framebuffer[ host_d_i[20:0] ] <= host_d_i[27:24];
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fb_rdata <= framebuffer[fb_raddr_next];
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end
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always @*
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if(x == r_xsize && y ==r_ysize)
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fb_raddr_next <= 0;
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else if (x == r_xsize && !y[0])
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fb_raddr_next <= fb_raddr - r_xsize;
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else if (fifo_we)
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fb_raddr_next <= fb_raddr + 1;
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else
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fb_raddr_next <= fb_raddr;
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always@(posedge clk_i)
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if(!r_enable || !rst_n_i)
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fb_raddr <= 0;
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else
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fb_raddr <= fb_raddr_next;
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always@(fb_rdata)
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case(fb_rdata)
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0 : pixel <= 24'h000000;
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1 : pixel <= 24'h000080;
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2 : pixel <= 24'h0000ff;
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3 : pixel <= 24'h008000;
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4 : pixel <= 24'h008080;
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5 : pixel <= 24'h00ff00;
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6 : pixel <= 24'h00ffff;
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7 : pixel <= 24'h800000;
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8 : pixel <= 24'h800080;
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9 : pixel <= 24'h808000;
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10 : pixel <= 24'h808080;
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11 : pixel <= 24'hc0c0c0;
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12 : pixel <= 24'hff0000;
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13 : pixel <= 24'hff00ff;
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14 : pixel <= 24'hffff00;
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15 : pixel <= 24'hffffff;
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default : pixel <= 24'h000000;
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endcase // case (fb_rdata)
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assign fifo_pixel_o = pixel;
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end // if (g_use_dpram)
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endgenerate
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always@(posedge clk_i)
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if(!rst_n_i)
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begin
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r_enable <= 0;
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end else if (host_wr_i) begin
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case(host_a_i)
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`REG_TEST_CTL: r_enable <= host_d_i[0];
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`REG_TEST_XSIZE: r_xsize <= host_d_i;
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`REG_TEST_YSIZE: r_ysize <= host_d_i;
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endcase // case (host_a_i)
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end
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assign test_enable_o = r_enable;
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endmodule // test_image_gen
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