55 lines
1.2 KiB
VHDL
55 lines
1.2 KiB
VHDL
library ieee;
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use ieee.STD_LOGIC_1164.all;
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use ieee.NUMERIC_STD.all;
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use work.gencores_pkg.all;
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entity spec_reset_gen is
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port (
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clk_sys_i : in std_logic;
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rst_pcie_n_a_i : in std_logic;
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rst_button_n_a_i : in std_logic;
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rst_n_o : out std_logic
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);
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end spec_reset_gen;
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architecture behavioral of spec_reset_gen is
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signal powerup_cnt : unsigned(7 downto 0) := x"00";
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signal button_synced_n : std_logic;
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signal pcie_synced_n : std_logic;
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signal powerup_n : std_logic := '0';
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begin -- behavioral
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U_EdgeDet_PCIe : gc_sync_ffs port map (
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clk_i => clk_sys_i,
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rst_n_i => '1',
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data_i => rst_pcie_n_a_i,
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ppulse_o => pcie_synced_n);
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U_Sync_Button : gc_sync_ffs port map (
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clk_i => clk_sys_i,
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rst_n_i => '1',
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data_i => rst_button_n_a_i,
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synced_o => button_synced_n);
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p_powerup_reset : process(clk_sys_i)
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begin
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if rising_edge(clk_sys_i) then
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if(powerup_cnt /= x"ff") then
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powerup_cnt <= powerup_cnt + 1;
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powerup_n <= '0';
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else
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powerup_n <= '1';
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end if;
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end if;
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end process;
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rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
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end behavioral;
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