Rename Control Unit signals
parent
909087453a
commit
621772845d
|
@ -44,38 +44,38 @@
|
||||||
|
|
||||||
module qm_control(
|
module qm_control(
|
||||||
/// Instruction from the decode stage
|
/// Instruction from the decode stage
|
||||||
input wire [5:0] opcode,
|
input wire [5:0] i_Opcode,
|
||||||
input wire [5:0] funct,
|
input wire [5:0] i_Function,
|
||||||
|
|
||||||
/// Control lines to the pipeline stages
|
/// Control lines to the pipeline stages
|
||||||
// Mux selecting the destination register for the register writeback
|
// Mux selecting the destination register for the register writeback
|
||||||
// 0 - RT
|
// 0 - RT
|
||||||
// 1 - RD
|
// 1 - RD
|
||||||
output wire reg_destination,
|
output wire co_RegDest,
|
||||||
// Mux selecting the source of the ALU B operand
|
// Mux selecting the source of the ALU B operand
|
||||||
// 0 - Value of RT register
|
// 0 - Value of RT register
|
||||||
// 1 - instruction Imediate part
|
// 1 - instruction Imediate part
|
||||||
output wire alu_source,
|
output wire co_ALUSource,
|
||||||
// ALU Control signal, select ALU operation
|
// ALU Control signal, select ALU operation
|
||||||
output wire [3:0] alu_control,
|
output wire [3:0] co_ALUControl,
|
||||||
// Memory write enable signal
|
// Memory write enable signal
|
||||||
output wire mem_write,
|
output wire co_MemWrite,
|
||||||
// Mux selecting the source of the data for the register writeback
|
// Mux selecting the source of the data for the register writeback
|
||||||
// 0 - output of ALU
|
// 0 - output of ALU
|
||||||
// 1 - data read from memory
|
// 1 - data read from memory
|
||||||
output wire reg_wsource,
|
output wire co_RegWSource,
|
||||||
// Register writeback enable signal
|
// Register writeback enable signal
|
||||||
output wire reg_write
|
output wire co_RegWrite
|
||||||
);
|
);
|
||||||
|
|
||||||
always @(opcode, funct) begin
|
always @(opcode, funct) begin
|
||||||
case (opcode)
|
case (opcode)
|
||||||
`OP_SPECIAL: begin
|
`OP_SPECIAL: begin
|
||||||
reg_destination <= 1;
|
co_RegDest <= 1;
|
||||||
alu_source <= 0;
|
co_ALUSource <= 0;
|
||||||
mem_write <= 0;
|
co_MemWrite <= 0;
|
||||||
reg_wsource <= 0;
|
co_RegWSource <= 0;
|
||||||
reg_write <= 1;
|
co_RegWrite <= 1;
|
||||||
case (funct)
|
case (funct)
|
||||||
`FUNCT_ADD: <= `ALU_ADD;
|
`FUNCT_ADD: <= `ALU_ADD;
|
||||||
`FUNCT_ADDU: <= `ALU_ADD;
|
`FUNCT_ADDU: <= `ALU_ADD;
|
||||||
|
@ -93,36 +93,36 @@ always @(opcode, funct) begin
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
`OP_LW: begin
|
`OP_LW: begin
|
||||||
reg_destination <= 0;
|
co_RegDest <= 0;
|
||||||
alu_source <= 1;
|
co_ALUSource <= 1;
|
||||||
alu_control <= 0;
|
co_ALUControl <= 0;
|
||||||
mem_write <= 0;
|
co_MemWrite <= 0;
|
||||||
reg_wsource <= 1;
|
co_RegWSource <= 1;
|
||||||
reg_write <= 1;
|
co_RegWrite <= 1;
|
||||||
end
|
end
|
||||||
`OP_SW: begin
|
`OP_SW: begin
|
||||||
reg_destination <= 0;
|
co_RegDest <= 0;
|
||||||
alu_source <= 1;
|
co_ALUSource <= 1;
|
||||||
alu_control <= 0;
|
co_ALUControl <= 0;
|
||||||
mem_write <= 1;
|
co_MemWrite <= 1;
|
||||||
reg_wsource <= 0;
|
co_RegWSource <= 0;
|
||||||
reg_write <= 0;
|
co_RegWrite <= 0;
|
||||||
end
|
end
|
||||||
6'b001???: // all immediate arith/logic
|
6'b001???: // all immediate arith/logic
|
||||||
default: begin
|
default: begin
|
||||||
reg_destination <= 0;
|
co_RegDest <= 0;
|
||||||
alu_source <= 0;
|
co_ALUSource <= 0;
|
||||||
mem_write <= 0;
|
co_MemWrite <= 0;
|
||||||
reg_wsource <= 0;
|
co_RegWSource <= 0;
|
||||||
reg_write <= 0;
|
co_RegWrite <= 0;
|
||||||
case (opcode)
|
case (opcode)
|
||||||
`OP_ADDI: alu_control <= `ALU_ADD;
|
`OP_ADDI: co_ALUControl <= `ALU_ADD;
|
||||||
`OP_ADDIU: alu_control <= `ALU_ADD;
|
`OP_ADDIU: co_ALUControl <= `ALU_ADD;
|
||||||
`OP_ANDI: alu_control <= `ALU_AND;
|
`OP_ANDI: co_ALUControl <= `ALU_AND;
|
||||||
`OP_ORI: alu_control <= `ALU_OR;
|
`OP_ORI: co_ALUControl <= `ALU_OR;
|
||||||
`OP_XORI: alu_control <= `ALU_XOR;
|
`OP_XORI: co_ALUControl <= `ALU_XOR;
|
||||||
`OP_SLTI: alu_control <= `ALU_SLT;
|
`OP_SLTI: co_ALUControl <= `ALU_SLT;
|
||||||
`OP_SLTIU: alu_control <= `ALU_SLTIU;
|
`OP_SLTIU: co_ALUControl <= `ALU_SLTIU;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
|
|
|
@ -1,24 +1,47 @@
|
||||||
module qm_decode(
|
module qm_decode(
|
||||||
/// datapath
|
/// datapath
|
||||||
// input instruction register
|
// from Fetch
|
||||||
input wire [31:0] di_IR,
|
input wire [31:0] di_IR,
|
||||||
// output instruction register
|
// backtraced from decode
|
||||||
output wire [31:0] do_IR,
|
input wire [4:0] di_WA,
|
||||||
// output first operand
|
input wire di_WE,
|
||||||
output wire [31:0] do_A,
|
input wire [31:0] di_WD
|
||||||
// output second operand
|
|
||||||
output wire [31:0] do_B,
|
|
||||||
// output immediate
|
|
||||||
output wire [31:0] do_Imm,
|
|
||||||
|
|
||||||
// control signals
|
output wire [31:0] do_RSVal,
|
||||||
|
output wire [31:0] do_RTVal,
|
||||||
// debug signals
|
output wire [31:0] do_Imm,
|
||||||
input wire [4:0] dbg_wa,
|
output wire [4:0] do_RS,
|
||||||
input wire dbg_we,
|
output wire [4:0] do_RT,
|
||||||
input wire [31:0] dbg_wd
|
|
||||||
|
/// instruction to control unit
|
||||||
|
output wire [5:0] o_Opcode,
|
||||||
|
output wire [5:0] o_Function,
|
||||||
|
|
||||||
|
/// controlpath
|
||||||
|
input wire ci_RegWrite,
|
||||||
|
input wire ci_RegWSource,
|
||||||
|
input wire ci_MemWrite,
|
||||||
|
input wire [3:0] ci_ALUControl,
|
||||||
|
input wire ci_ALUSource,
|
||||||
|
input wire ci_RegDest,
|
||||||
|
input wire ci_Branch,
|
||||||
|
|
||||||
|
output wire co_RegWrite,
|
||||||
|
output wire co_RegWSource,
|
||||||
|
output wire co_MemWrite,
|
||||||
|
output wire [3:0] co_ALUControl,
|
||||||
|
output wire co_ALUSource,
|
||||||
|
output wire co_RegDest
|
||||||
);
|
);
|
||||||
|
|
||||||
|
// passthrough
|
||||||
|
assign co_RegWrite = ci_RegWrite;
|
||||||
|
assign co_RegWSource = ci_RegWSource;
|
||||||
|
assign co_MemWrite = ci_MemWrite;
|
||||||
|
assign co_ALUControl = ci_ALUControl;
|
||||||
|
assign co_ALUSource = ci_ALUSource;
|
||||||
|
assign co_RegDest = ci_RegDest;
|
||||||
|
|
||||||
// internal signals from the IR
|
// internal signals from the IR
|
||||||
wire [4:0] rs;
|
wire [4:0] rs;
|
||||||
wire [4:0] rt;
|
wire [4:0] rt;
|
||||||
|
@ -31,18 +54,19 @@ assign imm = di_IR[15:0];
|
||||||
qm_regfile regfile(
|
qm_regfile regfile(
|
||||||
.ra1(rs),
|
.ra1(rs),
|
||||||
.ra2(rt),
|
.ra2(rt),
|
||||||
.rd1(do_A),
|
.rd1(do_RSVal),
|
||||||
.rd2(do_B),
|
.rd2(do_RTVal),
|
||||||
|
.wa3(di_WA),
|
||||||
// unused
|
.we3(di_WE),
|
||||||
.wa3(dbg_wa),
|
.wd3(di_WD)
|
||||||
.we3(dbg_we),
|
|
||||||
.wd3(dbg_wd)
|
|
||||||
);
|
);
|
||||||
|
|
||||||
// sign extend imm
|
// sign extend imm
|
||||||
assign do_Imm[31:0] = { {16{imm[15]}}, imm[15:0] };
|
assign do_Imm[31:0] = { {16{imm[15]}}, imm[15:0] };
|
||||||
|
assign do_RS = rs;
|
||||||
|
assign do_RT = rt;
|
||||||
|
|
||||||
assign do_IR = di_IR;
|
assign o_Opcode = di_IR[31:26];
|
||||||
|
assign o_Function = di_IR[5:0];
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
Loading…
Reference in New Issue