From 621772845de21b932710fe7cfe2aa22f86cc440f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sergiusz=20=27q3k=27=20Baza=C5=84ski?= Date: Tue, 16 Dec 2014 19:09:57 +0100 Subject: [PATCH] Rename Control Unit signals --- rtl/verilog/qm_control.v | 74 ++++++++++++++++++++-------------------- rtl/verilog/qm_decode.v | 70 ++++++++++++++++++++++++------------- 2 files changed, 84 insertions(+), 60 deletions(-) diff --git a/rtl/verilog/qm_control.v b/rtl/verilog/qm_control.v index a3ddc28..087442a 100644 --- a/rtl/verilog/qm_control.v +++ b/rtl/verilog/qm_control.v @@ -44,38 +44,38 @@ module qm_control( /// Instruction from the decode stage - input wire [5:0] opcode, - input wire [5:0] funct, + input wire [5:0] i_Opcode, + input wire [5:0] i_Function, /// Control lines to the pipeline stages // Mux selecting the destination register for the register writeback // 0 - RT // 1 - RD - output wire reg_destination, + output wire co_RegDest, // Mux selecting the source of the ALU B operand // 0 - Value of RT register // 1 - instruction Imediate part - output wire alu_source, + output wire co_ALUSource, // ALU Control signal, select ALU operation - output wire [3:0] alu_control, + output wire [3:0] co_ALUControl, // Memory write enable signal - output wire mem_write, + output wire co_MemWrite, // Mux selecting the source of the data for the register writeback // 0 - output of ALU // 1 - data read from memory - output wire reg_wsource, + output wire co_RegWSource, // Register writeback enable signal - output wire reg_write + output wire co_RegWrite ); always @(opcode, funct) begin case (opcode) `OP_SPECIAL: begin - reg_destination <= 1; - alu_source <= 0; - mem_write <= 0; - reg_wsource <= 0; - reg_write <= 1; + co_RegDest <= 1; + co_ALUSource <= 0; + co_MemWrite <= 0; + co_RegWSource <= 0; + co_RegWrite <= 1; case (funct) `FUNCT_ADD: <= `ALU_ADD; `FUNCT_ADDU: <= `ALU_ADD; @@ -93,36 +93,36 @@ always @(opcode, funct) begin endcase end `OP_LW: begin - reg_destination <= 0; - alu_source <= 1; - alu_control <= 0; - mem_write <= 0; - reg_wsource <= 1; - reg_write <= 1; + co_RegDest <= 0; + co_ALUSource <= 1; + co_ALUControl <= 0; + co_MemWrite <= 0; + co_RegWSource <= 1; + co_RegWrite <= 1; end `OP_SW: begin - reg_destination <= 0; - alu_source <= 1; - alu_control <= 0; - mem_write <= 1; - reg_wsource <= 0; - reg_write <= 0; + co_RegDest <= 0; + co_ALUSource <= 1; + co_ALUControl <= 0; + co_MemWrite <= 1; + co_RegWSource <= 0; + co_RegWrite <= 0; end 6'b001???: // all immediate arith/logic default: begin - reg_destination <= 0; - alu_source <= 0; - mem_write <= 0; - reg_wsource <= 0; - reg_write <= 0; + co_RegDest <= 0; + co_ALUSource <= 0; + co_MemWrite <= 0; + co_RegWSource <= 0; + co_RegWrite <= 0; case (opcode) - `OP_ADDI: alu_control <= `ALU_ADD; - `OP_ADDIU: alu_control <= `ALU_ADD; - `OP_ANDI: alu_control <= `ALU_AND; - `OP_ORI: alu_control <= `ALU_OR; - `OP_XORI: alu_control <= `ALU_XOR; - `OP_SLTI: alu_control <= `ALU_SLT; - `OP_SLTIU: alu_control <= `ALU_SLTIU; + `OP_ADDI: co_ALUControl <= `ALU_ADD; + `OP_ADDIU: co_ALUControl <= `ALU_ADD; + `OP_ANDI: co_ALUControl <= `ALU_AND; + `OP_ORI: co_ALUControl <= `ALU_OR; + `OP_XORI: co_ALUControl <= `ALU_XOR; + `OP_SLTI: co_ALUControl <= `ALU_SLT; + `OP_SLTIU: co_ALUControl <= `ALU_SLTIU; endcase end endcase diff --git a/rtl/verilog/qm_decode.v b/rtl/verilog/qm_decode.v index bc276de..c8d3568 100644 --- a/rtl/verilog/qm_decode.v +++ b/rtl/verilog/qm_decode.v @@ -1,24 +1,47 @@ module qm_decode( /// datapath - // input instruction register + // from Fetch input wire [31:0] di_IR, - // output instruction register - output wire [31:0] do_IR, - // output first operand - output wire [31:0] do_A, - // output second operand - output wire [31:0] do_B, - // output immediate - output wire [31:0] do_Imm, + // backtraced from decode + input wire [4:0] di_WA, + input wire di_WE, + input wire [31:0] di_WD - // control signals - - // debug signals - input wire [4:0] dbg_wa, - input wire dbg_we, - input wire [31:0] dbg_wd + output wire [31:0] do_RSVal, + output wire [31:0] do_RTVal, + output wire [31:0] do_Imm, + output wire [4:0] do_RS, + output wire [4:0] do_RT, + + /// instruction to control unit + output wire [5:0] o_Opcode, + output wire [5:0] o_Function, + + /// controlpath + input wire ci_RegWrite, + input wire ci_RegWSource, + input wire ci_MemWrite, + input wire [3:0] ci_ALUControl, + input wire ci_ALUSource, + input wire ci_RegDest, + input wire ci_Branch, + + output wire co_RegWrite, + output wire co_RegWSource, + output wire co_MemWrite, + output wire [3:0] co_ALUControl, + output wire co_ALUSource, + output wire co_RegDest ); +// passthrough +assign co_RegWrite = ci_RegWrite; +assign co_RegWSource = ci_RegWSource; +assign co_MemWrite = ci_MemWrite; +assign co_ALUControl = ci_ALUControl; +assign co_ALUSource = ci_ALUSource; +assign co_RegDest = ci_RegDest; + // internal signals from the IR wire [4:0] rs; wire [4:0] rt; @@ -31,18 +54,19 @@ assign imm = di_IR[15:0]; qm_regfile regfile( .ra1(rs), .ra2(rt), - .rd1(do_A), - .rd2(do_B), - - // unused - .wa3(dbg_wa), - .we3(dbg_we), - .wd3(dbg_wd) + .rd1(do_RSVal), + .rd2(do_RTVal), + .wa3(di_WA), + .we3(di_WE), + .wd3(di_WD) ); // sign extend imm assign do_Imm[31:0] = { {16{imm[15]}}, imm[15:0] }; +assign do_RS = rs; +assign do_RT = rt; -assign do_IR = di_IR; +assign o_Opcode = di_IR[31:26]; +assign o_Function = di_IR[5:0]; endmodule