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Fix always comb logic outputs 

This makes iverilog happy

Signed-off-by: Sergiusz 'q3k' Bazański <q3k@q3k.org>
master
q3k 2014-12-17 18:38:12 +01:00
parent 7b562944ca
commit 4c76928b28
5 changed files with 118 additions and 103 deletions
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125
rtl/verilog/qm_control.v
View File

@ -75,86 +75,95 @@ module qm_control(
// Mux selecting the destination register for the register writeback // Mux selecting the destination register for the register writeback
// 0 - RT // 0 - RT
// 1 - RD // 1 - RD
output wire co_RegDest, output reg co_RegDest,
// Mux selecting the source of the ALU B operand // Mux selecting the source of the ALU B operand
// 0 - Value of RT register // 0 - Value of RT register
// 1 - instruction Imediate part // 1 - instruction Imediate part
output wire co_ALUSource, output reg co_ALUSource,
// ALU Control signal, select ALU operation // ALU Control signal, select ALU operation
output wire [3:0] co_ALUControl, output reg [3:0] co_ALUControl,
// Memory write enable signal // Memory write enable signal
output wire co_MemWrite, output reg co_MemWrite,
// Mux selecting the source of the data for the register writeback // Mux selecting the source of the data for the register writeback
// 0 - output of ALU // 0 - output of ALU
// 1 - data read from memory // 1 - data read from memory
output wire co_RegWSource, output reg co_RegWSource,
// Register writeback enable signal // Register writeback enable signal
output wire co_RegWrite, output reg co_RegWrite,
// Unused... // Unused...
output wire co_Branch output reg co_Branch
); );
always @(opcode, funct) begin always @(i_Opcode, i_Function) begin
case (opcode) case (i_Opcode)
`OP_SPECIAL: begin `OP_SPECIAL: begin
co_RegDest <= 1; co_RegDest = 1;
co_ALUSource <= 0; co_ALUSource = 0;
co_MemWrite <= 0; co_MemWrite = 0;
co_RegWSource <= 0; co_RegWSource = 0;
co_RegWrite <= 1; co_RegWrite = 1;
co_Branch <= 0; co_Branch = 0;
case (funct) case (i_Function)
`FUNCT_ADD: <= `ALU_ADD; `FUNCT_ADD: co_ALUControl = `ALU_ADD;
`FUNCT_ADDU: <= `ALU_ADD; `FUNCT_ADDU: co_ALUControl = `ALU_ADD;
`FUNCT_AND: <= `ALU_AND; `FUNCT_AND: co_ALUControl = `ALU_AND;
`FUNCT_DIV: <= `ALU_DIV; `FUNCT_DIV: co_ALUControl = `ALU_DIV;
`FUNCT_DIVU: <= `ALU_DIV; `FUNCT_DIVU: co_ALUControl = `ALU_DIV;
`FUNCT_MULT: <= `ALU_MUL; `FUNCT_MULT: co_ALUControl = `ALU_MUL;
`FUNCT_MULTU: <= `ALU_MUL; `FUNCT_MULTU: co_ALUControl = `ALU_MUL;
`FUNCT_NOR: <= `ALU_NOR `FUNCT_NOR: co_ALUControl = `ALU_NOR;
`FUNCT_OR: <= `ALU_OR; `FUNCT_OR: co_ALUControl = `ALU_OR;
`FUNCT_SLT: <= `ALU_SLT; `FUNCT_SLT: co_ALUControl = `ALU_SLT;
`FUNCT_SUB: <= `ALU_SUB; `FUNCT_SUB: co_ALUControl = `ALU_SUB;
`FUNCT_SUBU: <= `ALU_SUB; `FUNCT_SUBU: co_ALUControl = `ALU_SUB;
`FUNCT_XOR: <= `ALU_XOR; `FUNCT_XOR: co_ALUControl = `ALU_XOR;
endcase endcase
end end
`OP_LW: begin `OP_LW: begin
co_RegDest <= 0; co_RegDest = 0;
co_ALUSource <= 1; co_ALUSource = 1;
co_ALUControl <= 0; co_ALUControl = 0;
co_MemWrite <= 0; co_MemWrite = 0;
co_RegWSource <= 1; co_RegWSource = 1;
co_RegWrite <= 1; co_RegWrite = 1;
co_Branch <= 0; co_Branch = 0;
end end
`OP_SW: begin `OP_SW: begin
co_RegDest <= 0; co_RegDest = 0;
co_ALUSource <= 1; co_ALUSource = 1;
co_ALUControl <= 0; co_ALUControl = 0;
co_MemWrite <= 1; co_MemWrite = 1;
co_RegWSource <= 0; co_RegWSource = 0;
co_RegWrite <= 0; co_RegWrite = 0;
co_Branch <= 0; co_Branch = 0;
end end
6'b001???: // all immediate arith/logic 6'b001???: // all immediate arith/logic
default: begin begin
co_RegDest <= 0; co_RegDest = 0;
co_ALUSource <= 0; co_ALUSource = 1;
co_MemWrite <= 0; co_MemWrite = 0;
co_RegWSource <= 0; co_RegWSource = 0;
co_RegWrite <= 0; co_RegWrite = 1;
co_Branch <= 0; co_Branch = 0;
case (opcode) case (i_Opcode)
`OP_ADDI: co_ALUControl <= `ALU_ADD; `OP_ADDI: co_ALUControl = `ALU_ADD;
`OP_ADDIU: co_ALUControl <= `ALU_ADD; `OP_ADDIU: co_ALUControl = `ALU_ADD;
`OP_ANDI: co_ALUControl <= `ALU_AND; `OP_ANDI: co_ALUControl = `ALU_AND;
`OP_ORI: co_ALUControl <= `ALU_OR; `OP_ORI: co_ALUControl = `ALU_OR;
`OP_XORI: co_ALUControl <= `ALU_XOR; `OP_XORI: co_ALUControl = `ALU_XOR;
`OP_SLTI: co_ALUControl <= `ALU_SLT; `OP_SLTI: co_ALUControl = `ALU_SLT;
`OP_SLTIU: co_ALUControl <= `ALU_SLTIU; `OP_SLTIU: co_ALUControl = `ALU_SLT;
endcase endcase
end end
default: begin
co_RegDest = 0;
co_ALUSource = 1;
co_MemWrite = 0;
co_RegWSource = 0;
co_RegWrite = 0;
co_Branch = 0;
co_ALUControl = 0;
end
endcase endcase
end end

2
rtl/verilog/qm_decode.v
View File

@ -22,6 +22,8 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
`include "qm_regfile.v"
/* verilator lint_off UNUSED */ /* verilator lint_off UNUSED */
module qm_decode( module qm_decode(
/// datapath /// datapath

4
rtl/verilog/qm_fetch.v
View File

@ -27,9 +27,9 @@ module qm_fetch(
// input PC to assume // input PC to assume
input wire [31:0] di_PC, input wire [31:0] di_PC,
// output instruction register // output instruction register
output wire [31:0] do_IR, output reg [31:0] do_IR,
// output to next PC // output to next PC
output wire [31:0] do_NextPC, output reg [31:0] do_NextPC,
// icache connectivity // icache connectivity
output wire [31:0] icache_address, output wire [31:0] icache_address,

16
rtl/verilog/qm_icache.v
View File

@ -29,24 +29,24 @@ module qm_icache(
input wire clk, input wire clk,
// to the consumer (CPU fetch stage) // to the consumer (CPU fetch stage)
output wire hit, output reg hit,
output wire stall, output reg stall,
output wire [31:0] data, output reg [31:0] data,
input wire enable, input wire enable,
// to the memory controller (no wishbone yet...) // to the memory controller (no wishbone yet...)
// the cache is currently only backed in 1GBit RAM via this controller // the cache is currently only backed in 1GBit RAM via this controller
// this RAM is mapped 0x80000000 - 0x90000000 // this RAM is mapped 0x80000000 - 0x90000000
output wire mem_cmd_clk, // we will keep this synchronous to the input clock output wire mem_cmd_clk, // we will keep this synchronous to the input clock
output wire mem_cmd_en, output reg mem_cmd_en,
output wire [2:0] mem_cmd_instr, output reg [2:0] mem_cmd_instr,
output wire [5:0] mem_cmd_bl, output reg [5:0] mem_cmd_bl,
output wire [29:0] mem_cmd_addr, output reg [29:0] mem_cmd_addr,
input wire mem_cmd_full, input wire mem_cmd_full,
input wire mem_cmd_empty, input wire mem_cmd_empty,
output wire mem_rd_clk, output wire mem_rd_clk,
output wire mem_rd_en, output reg mem_rd_en,
input wire [6:0] mem_rd_count, input wire [6:0] mem_rd_count,
input wire mem_rd_full, input wire mem_rd_full,
input wire [31:0] mem_rd_data, input wire [31:0] mem_rd_data,

74
rtl/verilog/qm_top.v
View File

@ -22,8 +22,13 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
`include "qm_control.v"
`include "qm_icache.v"
`include "qm_fetch.v"
`include "qm_decode.v"
module qm_top( module qm_top(
input wire clk
); );
/// Controlpath signal inputs /// Controlpath signal inputs
@ -36,12 +41,12 @@ reg DEC_ALUSource;
reg DEC_RegDest; reg DEC_RegDest;
/// Controlpath signal outputs /// Controlpath signal outputs
reg cdecode_RegWrite; wire cdecode_RegWrite;
reg cdecode_RegWSource; wire cdecode_RegWSource;
reg cdecode_MemWrite; wire cdecode_MemWrite;
reg [3:0] cdecode_ALUControl; wire [3:0] cdecode_ALUControl;
reg cdecode_ALUSource; wire cdecode_ALUSource;
reg cdecode_RegDest; wire cdecode_RegDest;
/// Datapath signal inputs /// Datapath signal inputs
// Fetch / Decode // Fetch / Decode
@ -86,7 +91,7 @@ always @(posedge clk) begin
DE_RT <= decode_RT; DE_RT <= decode_RT;
DEC_RegWrite <= cdecode_RegWrite; DEC_RegWrite <= cdecode_RegWrite;
DEC_REGWSource <= cdecode_RegWSource; DEC_RegWSource <= cdecode_RegWSource;
DEC_MemWrite <= cdecode_MemWrite; DEC_MemWrite <= cdecode_MemWrite;
DEC_ALUControl <= cdecode_ALUControl; DEC_ALUControl <= cdecode_ALUControl;
DEC_ALUSource <= cdecode_ALUSource; DEC_ALUSource <= cdecode_ALUSource;
@ -104,16 +109,16 @@ wire control_RegWSource;
wire control_RegWrite; wire control_RegWrite;
wire control_Branch; wire control_Branch;
qm_control control( qm_control control(
i_Opcode(decode_Opcode), .i_Opcode(decode_Opcode),
i_Function(decode_Function), .i_Function(decode_Function),
co_RegDest(control_RegDest), .co_RegDest(control_RegDest),
co_ALUSource(control_ALUSource), .co_ALUSource(control_ALUSource),
co_ALUControl(control_ALUControl), .co_ALUControl(control_ALUControl),
co_MemWrite(control_MemWrite), .co_MemWrite(control_MemWrite),
co_RegWSource(control_RegWSource), .co_RegWSource(control_RegWSource),
co_RegWrite(control_RegWrite), .co_RegWrite(control_RegWrite),
co_Branch(control_Branch) .co_Branch(control_Branch)
); );
// ICache // ICache
qm_icache icache( qm_icache icache(
@ -147,27 +152,26 @@ qm_decode decode(
.do_RS(decode_RS), .do_RS(decode_RS),
.do_RT(decode_RT), .do_RT(decode_RT),
di_WA(0), .di_WA(0),
di_WE(0), .di_WE(0),
di_WD(0), .di_WD(0),
o_Opcode(decode_Opcode), .o_Opcode(decode_Opcode),
o_Function(decode_Function), .o_Function(decode_Function),
ci_RegWrite(control_RegWrite), .ci_RegWrite(control_RegWrite),
ci_RegWSource(control_RegWSource), .ci_RegWSource(control_RegWSource),
ci_MemWrite(control_MemWrite), .ci_MemWrite(control_MemWrite),
ci_ALUControl(control_ALUControl), .ci_ALUControl(control_ALUControl),
ci_ALUSource(control_ALUSource), .ci_ALUSource(control_ALUSource),
ci_RegDest(control_RegDest), .ci_RegDest(control_RegDest),
co_RegDest(cdecode_RegDest), .co_RegDest(cdecode_RegDest),
co_ALUSource(cdecode_ALUSource), .co_ALUSource(cdecode_ALUSource),
co_ALUControl(cdecode_ALUControl), .co_ALUControl(cdecode_ALUControl),
co_MemWrite(cdecode_MemWrite), .co_MemWrite(cdecode_MemWrite),
co_RegWSource(cdecode_RegWSource), .co_RegWSource(cdecode_RegWSource),
co_RegWrite(cdecode_RegWrite), .co_RegWrite(cdecode_RegWrite)
); );
endmodule endmodule