49 lines
884 B
Verilog
49 lines
884 B
Verilog
module qm_decode(
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/// datapath
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// input instruction register
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input wire [31:0] di_IR,
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// output instruction register
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output wire [31:0] do_IR,
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// output first operand
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output wire [31:0] do_A,
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// output second operand
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output wire [31:0] do_B,
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// output immediate
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output wire [31:0] do_Imm,
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// control signals
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// debug signals
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input wire [4:0] dbg_wa,
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input wire dbg_we,
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input wire [31:0] dbg_wd
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);
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// internal signals from the IR
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wire [4:0] rs;
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wire [4:0] rt;
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wire [15:0] imm;
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assign rs = di_IR[25:21];
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assign rt = di_IR[20:16];
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assign imm = di_IR[15:0];
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qm_regfile regfile(
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.ra1(rs),
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.ra2(rt),
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.rd1(do_A),
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.rd2(do_B),
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// unused
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.wa3(dbg_wa),
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.we3(dbg_we),
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.wd3(dbg_wd)
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);
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// sign extend imm
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assign do_Imm[31:0] = { {16{imm[15]}}, imm[15:0] };
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assign do_IR = di_IR;
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endmodule
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