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57
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Verilog
72.2%
C++
18.7%
C
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Makefile
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1797089f79
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q3k
1797089f79
First commit.
2014-09-07 15:48:43 +02:00
rtl
/verilog
First commit.
2014-09-07 15:48:43 +02:00
test
First commit.
2014-09-07 15:48:43 +02:00
.gitignore
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2014-09-07 15:48:43 +02:00