456 lines
12 KiB
Verilog
456 lines
12 KiB
Verilog
/*
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* DSI Core
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* Copyright (C) 2013 twl <twlostow@printf.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 3.0 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library.
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*/
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`include "dsi_defs.vh"
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`timescale 1ns/1ps
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/*
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* dsi_core.v
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*
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* Top level of the core. Currently works on Spartan-6 FPGAs only.
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*/
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module dsi_core
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(
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// system clock (= pixel clock for the moment)
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clk_sys_i,
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// PHY serdes clock (= 8x pixel clock)
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clk_phy_i,
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rst_n_i,
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pll_locked_i,
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frame_ready_o,
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// Pixel FIFO interface
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fifo_full_o,
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fifo_pixels_i,
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fifo_frame_i,
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fifo_wr_i,
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// DSI high speed output (OSERDES2)
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dsi_hs_p_o,
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dsi_hs_n_o,
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// DSI low power output
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dsi_lp_p_o,
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dsi_lp_n_o,
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// Lop power output enable
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dsi_lp_oe_o,
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// DSI clock lane output
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dsi_clk_p_o,
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dsi_clk_n_o,
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// DSI clock lane LP signals + output enable
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dsi_clk_lp_p_o,
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dsi_clk_lp_n_o,
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dsi_clk_lp_oe_o,
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// Displat reset pin
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dsi_reset_n_o,
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// Host control registers
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host_a_i,
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host_d_i,
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host_d_o,
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host_wr_i
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);
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parameter g_pixels_per_clock = 1;
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parameter g_lanes = 3;
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parameter g_fifo_size = 1024;
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parameter g_invert_lanes = 0;
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parameter g_invert_clock = 0;
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localparam g_pixel_width = 24 * g_pixels_per_clock;
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input clk_sys_i, clk_phy_i, rst_n_i;
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input pll_locked_i;
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output frame_ready_o;
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output fifo_full_o;
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input [g_pixel_width - 1 : 0 ] fifo_pixels_i;
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input fifo_frame_i, fifo_wr_i;
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output dsi_clk_p_o, dsi_clk_n_o;
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output [g_lanes-1:0] dsi_hs_p_o, dsi_hs_n_o;
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output [g_lanes-1:0] dsi_lp_p_o, dsi_lp_n_o;
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output [g_lanes-1:0] dsi_lp_oe_o;
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output dsi_clk_lp_p_o, dsi_clk_lp_n_o;
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output dsi_clk_lp_oe_o;
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output reg dsi_reset_n_o;
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input [5:0] host_a_i;
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input [31:0] host_d_i;
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output [31:0] host_d_o;
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input host_wr_i;
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///////////////////
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// PHY/Serdes layer
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///////////////////
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reg tick = 0;
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wire [g_lanes-1:0] phy_hs_ready_lane, lp_ready_lane, lp_readback_lane;
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wire [g_lanes:0] serdes_oe_lane;
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wire [g_lanes-1:0] lp_txp, lp_txn, lp_oe;
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wire lp_ready;
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wire phy_hs_ready;
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assign lp_ready = lp_ready_lane[0];
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assign phy_hs_ready = phy_hs_ready_lane[0];
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wire phy_hs_request;
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wire [g_lanes * 8 -1 :0] phy_hs_data;
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wire [g_lanes-1:0] phy_hs_valid;
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wire [(g_lanes + 1) * 8 - 1: 0] serdes_data, serdes_data_interleaved;
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reg r_dsi_clk_en = 0;
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reg lp_request = 0;
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reg lp_valid = 0;
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reg [7:0] lp_data = 0;
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generate
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genvar i;
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for(i=0;i<g_lanes;i=i+1)
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begin
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dphy_lane
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#(
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.g_invert(g_invert_lanes&(1<<i)?1:0)
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)
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U_LaneX
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(
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.clk_i(clk_sys_i),
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.rst_n_i(rst_n_i),
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.tick_i(tick),
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.hs_request_i (phy_hs_request),
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.hs_data_i (phy_hs_data[ (g_lanes-i) *8-1 -:8]), // >> ((g_lanes - 1 - i)*8)}),
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.hs_ready_o (phy_hs_ready_lane[i]),
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.hs_valid_i(phy_hs_valid[i]),
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.lp_request_i (lp_request),
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.lp_data_i (lp_data),
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.lp_valid_i (i ==0 ? lp_valid : 1'b0),
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.lp_ready_o (lp_ready_lane[i]),
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.serdes_data_o(serdes_data[i*8+:8]),
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.lp_txp_o(lp_txp[i]),
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.lp_txn_o(lp_txn[i]),
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.lp_oe_o(lp_oe[i])
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);
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assign dsi_lp_p_o[i] = lp_txp[i];
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assign dsi_lp_n_o[i] = lp_txn[i];
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assign dsi_lp_oe_o[i] = lp_oe[0];
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assign serdes_oe_lane[i] = ~lp_oe[0];
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end // for (i=0;i<g_lanes;i=i+1)
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endgenerate
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wire clk_lane_ready;
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wire dsi_clk_lp_oe;
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dphy_lane
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#(
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.g_invert(g_invert_clock)
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) U_ClockLane (
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.clk_i(clk_sys_i),
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.rst_n_i(rst_n_i),
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.tick_i(tick),
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.hs_request_i (r_dsi_clk_en),
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.hs_data_i (clk_lane_ready ? 8'haa : 8'h00),
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.hs_ready_o (clk_lane_ready),
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.hs_valid_i(1'b1),
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.lp_request_i (1'b0),
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.lp_data_i(8'h00),
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.lp_valid_i(1'b0),
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.lp_ready_o(),
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.serdes_data_o(serdes_data[g_lanes*8+:8]),
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.lp_txp_o(dsi_clk_lp_p_o),
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.lp_txn_o(dsi_clk_lp_n_o),
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.lp_oe_o(dsi_clk_lp_oe)
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);
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assign serdes_oe_lane [g_lanes] = ~dsi_clk_lp_oe;
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assign dsi_clk_lp_oe_o = dsi_clk_lp_oe;
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generate
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genvar gi, gj;
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for(gi=0;gi<8;gi=gi+1)
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begin
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assign serdes_data_interleaved[(g_lanes+1)*gi+g_lanes] = serdes_data[8*g_lanes+gi];
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for(gj=0;gj<g_lanes; gj=gj+1)
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begin
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assign serdes_data_interleaved[(g_lanes+1)*gi+gj] = serdes_data[8*gj+gi];
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end
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end
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endgenerate
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dphy_serdes
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#(
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.sys_w (g_lanes + 1) ,
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.dev_w (g_lanes * 8 + 8)
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) U_Serdes (
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.DATA_OUT_FROM_DEVICE(serdes_data_interleaved),
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.DATA_OUT_TO_PINS_P({dsi_clk_p_o, dsi_hs_p_o }),
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.DATA_OUT_TO_PINS_N({dsi_clk_n_o, dsi_hs_n_o }),
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.CLK_IN(clk_phy_i),
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.CLK_DIV_IN(clk_sys_i),
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.LOCKED_IN(pll_locked_i),
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.CLK_RESET(~rst_n_i),
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.IO_RESET(~rst_n_i),
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.OE(serdes_oe_lane));
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////////////////
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// Packet layer
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///////////////
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wire p_req, p_islong, p_dreq, p_last;
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wire [5:0] p_type;
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wire [15:0] p_command, p_wcount;
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wire [g_pixel_width-1:0] p_payload;
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dsi_packet_assembler
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#(
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.g_num_lanes(g_lanes),
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.g_bytes_per_clock(g_pixels_per_clock)
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) U_PktAsm (
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.clk_i(clk_sys_i),
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.rst_n_i(rst_n_i),
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.p_req_i(p_req),
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.p_islong_i(p_islong),
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.p_type_i(p_type),
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.p_wcount_i(p_wcount),
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.p_command_i(p_command),
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.p_dreq_o(p_dreq),
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.p_dlast_o(p_dlast),
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.p_payload_i(p_payload),
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.p_last_i(p_last),
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.phy_d_o(phy_hs_data),
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.phy_hs_request_o(phy_hs_request),
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.phy_hs_dreq_i(phy_hs_ready_lane[0]),
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.phy_dvalid_o(phy_hs_valid)
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);
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////////////////
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// Test Screen generator
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///////////////
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wire fifo_frame_tgen, fifo_wr_tgen;
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wire [g_pixel_width-1:0] fifo_pixel_tgen;
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wire fifo_empty, fifo_rd;
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wire [g_pixel_width:0] fifo_dout;
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wire fifo_frame_int, fifo_wr_int, fifo_full_int;
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wire [g_pixel_width-1:0] fifo_pixels_int;
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wire tgen_enable;
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dsi_test_image_gen
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U_TestImgGen
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(
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.clk_i(clk_sys_i),
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.rst_n_i(rst_n_i),
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.fifo_full_i(fifo_full_int),
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.fifo_frame_o(fifo_frame_tgen),
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.fifo_pixel_o(fifo_pixel_tgen),
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.fifo_we_o(fifo_wr_tgen),
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.host_a_i(host_a_i),
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.host_d_i(host_d_i),
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.host_wr_i(host_wr_i),
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.test_enable_o(tgen_enable)
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);
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assign fifo_frame_int = (tgen_enable ? fifo_frame_tgen : fifo_frame_i);
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assign fifo_pixels_int = (tgen_enable ? fifo_pixel_tgen : fifo_pixels_i);
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assign fifo_wr_int = (tgen_enable ? fifo_wr_tgen : fifo_wr_i);
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assign fifo_full_o = fifo_full_int;
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reg fifo_rd_d0, fifo_got_frame;
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///////////////
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// Image timing
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///////////////
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dsi_timing_gen U_TimingGen
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(
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.clk_i(clk_sys_i),
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.rst_n_i(rst_n_i),
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.fifo_empty_i(fifo_empty),
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.fifo_rd_o(fifo_rd),
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.fifo_pixels_i(fifo_dout[g_pixel_width-1:0]),
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.fifo_frame_i(fifo_dout[g_pixel_width]),
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.fifo_got_frame_i(fifo_got_frame),
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.p_req_o(p_req),
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.p_islong_o(p_islong),
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.p_type_o(p_type),
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.p_wcount_o(p_wcount),
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.p_command_o(p_command),
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.p_payload_o(p_payload),
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.p_dreq_i(p_dreq),
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.p_last_o(p_last),
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.host_a_i(host_a_i),
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.host_d_i(host_d_i),
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// .host_d_o(host_d_o),
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.host_wr_i(host_wr_i)
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);
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////////////////
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/// Pixel Buffer
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////////////////
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dsi_fifo #(
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.g_width(g_pixel_width + 1),
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.g_size(g_fifo_size)
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) U_PixFifo (
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.clk_i(clk_sys_i),
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.rst_n_i(rst_n_i),
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.d_i({fifo_frame_int, fifo_pixels_int}),
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.we_i(fifo_wr_int),
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.full_o(fifo_full_int),
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.q_o(fifo_dout),
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.rd_i(fifo_rd),
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.empty_o(fifo_empty)
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);
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always@(posedge clk_sys_i)
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if(!rst_n_i)
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begin
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fifo_rd_d0 <= 0;
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fifo_got_frame <= 0;
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end else begin
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fifo_rd_d0 <= fifo_rd;
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if(fifo_wr_int && fifo_frame_int)
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fifo_got_frame <= 1;
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else if (fifo_rd && fifo_dout[g_pixel_width])
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fifo_got_frame <= 0;
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end // else: !if(!rst_n_i)
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////////////////
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// Host regs
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////////////////
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reg [11:0] r_tick_div, tick_count;
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always@(posedge clk_sys_i)
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begin
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if (!rst_n_i)
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tick_count <= 0;
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else begin
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if(tick_count == r_tick_div)
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begin
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tick <= 1;
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tick_count <= 0;
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end else begin
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tick <= 0;
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tick_count <= tick_count + 1;
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end
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end // else: !if(!rst_n_i)
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end // always@ (posedge clk_sys_i)
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reg [31:0] host_d_self;
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always@(posedge clk_sys_i)
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if(!rst_n_i)
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begin
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r_tick_div <= 0;
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r_dsi_clk_en <= 0;
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lp_request <= 0;
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host_d_self <= 0;
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dsi_reset_n_o <= 0;
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end else if(host_wr_i) begin
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case(host_a_i)
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`REG_TICK_DIV: r_tick_div <= host_d_i;
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`REG_DSI_CTL: begin
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r_dsi_clk_en <= host_d_i[0];
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lp_request <= host_d_i[1];
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end
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`REG_LP_TX:
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if(lp_ready) begin
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lp_valid <= host_d_i[8];
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lp_data <= host_d_i[7:0];
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end
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`REG_GPIO: begin
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dsi_reset_n_o <= host_d_i[0];
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end
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endcase // case (host_a_i)
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end else begin
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lp_valid <= 0;
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case(host_a_i)
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`REG_DSI_CTL: begin
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host_d_self[0] <= r_dsi_clk_en;
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host_d_self[31:2] <= 0;
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host_d_self[1] <= lp_ready;
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end
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default:
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host_d_self <= 0;
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endcase // case (host_a_i)
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end // else: !if(host_wr_i)
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assign host_d_o = host_d_self;
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endmodule // dsi_core
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