202 lines
6.3 KiB
Verilog
202 lines
6.3 KiB
Verilog
// Copyright (c) 2014 Sergiusz 'q3k' Bazański <sergiusz@bazanski.pl>
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// Licensed under 2-clause BSD - see COPYING file from software distribution
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`timescale 1ns / 1ps
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/* verilator lint_off UNDRIVEN */
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/* verilator lint_off UNUSED */
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/* verilator lint_off LITENDIAN */
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module cpu (
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input reset,
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input cpu_clock,
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input [15:0] keypad
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);
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// 4k (12 bits) of 8-bit ram
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reg [7:0] ram[0:4095]/* verilator public */;
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// 16 8-bit V registers
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reg [7:0] vr[0:15]/* verilator public */;
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// 16-bit I register
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reg [15:0] i;
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// 12-bit program counter
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reg [11:0] pc/* verilator public */;
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// 16-element, 12-bit stack
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reg [11:0] stack [0:15];
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// 4-bit stack pointer
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reg [3:0] sp;
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// internal cycle counter (0 - fetch)
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`define FETCH 0
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`define EXECUTE 1
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`define WRITEBACK 2
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reg [1:0] c;
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// Instruction register
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reg [15:0] ins;
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wire [3:0] family = ins[15:12];
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// ALU operation
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wire [3:0] alu_op = ins[3:0];
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wire is_alu_op = (c == `EXECUTE) && (family == 8);
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// Source register indexes
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wire [3:0] x = ins[11:8];
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wire [3:0] y = ins[7:4];
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// Immediates
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wire [7:0] kk = ins[7:0];
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wire [11:0] nnn = ins[11:0];
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// Jump register
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reg[11:0] jmp;
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// Should jump on FETCH?
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reg should_jmp;
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always @(posedge cpu_clock)
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begin
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if (!reset) begin
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i <= 0;
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pc <= 0;
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sp <= 0;
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should_jmp <= 0;
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c <= 0;
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vr[0] <= 0;
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vr[1] <= 0;
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vr[2] <= 0;
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vr[3] <= 0;
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vr[4] <= 0;
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vr[5] <= 0;
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vr[6] <= 0;
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vr[7] <= 0;
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vr[8] <= 0;
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vr[9] <= 0;
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vr[10] <= 0;
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vr[11] <= 0;
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vr[12] <= 0;
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vr[13] <= 0;
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vr[14] <= 0;
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vr[15] <= 0;
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end else begin
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case(c)
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`FETCH: begin
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ins <= {ram[pc], ram[pc + 1]};
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c <= 1;
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end
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`EXECUTE: begin
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case (family)
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// Jump to address
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1: begin
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should_jmp <= 1;
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jmp <= nnn;
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end
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// Call address
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2: begin
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should_jmp <= 1;
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stack[sp] <= pc;
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sp <= sp + 1;
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jmp <= nnn;
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end
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// Skip next if Vx == kk (3xkk)
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3: begin
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if (vr[x] == kk) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Skip next if Vx != kk (4xkk)
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4: begin
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if (vr[x] != kk) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Skip next if Vx == Vy (5xy0)
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5: begin
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if (vr[x] == vr[y]) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Vx <= kk
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6: vr[x] <= kk;
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// Vx += kk
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7: vr[x] <= vr[x] + kk;
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// Skip if Vx != Vy (9xy0)
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9: begin
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if (vr[x] != vr[y]) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Set I to nnn
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10: i <= {4'h0, nnn};
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// Jump to nnn + V0
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11: begin
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should_jmp <= 1;
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jmp <= nnn + {4'h0, vr[0]};
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end
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// Set Vx to random and kk
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// TODO: undo fair dice roll
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12: vr[x] <= 42 & kk;
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// TODO: draw sprites
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13: begin end
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// Key functions
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14: begin
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if (kk == 8'h9E) begin
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if (keypad[x]) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end else if (kk == 8'hA1) begin
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if (~keypad[x]) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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end
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endcase
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c <= 2;
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end
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`WRITEBACK: begin
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if (should_jmp) begin
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pc <= jmp;
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end else begin
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pc <= pc + 2;
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end
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should_jmp <= 0;
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c <= 0;
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end
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endcase
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end
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end
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// ALU
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always @(posedge cpu_clock)
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begin
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if (is_alu_op) begin
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case(alu_op)
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0: vr[x] <= vr[y];
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1: vr[x] <= vr[x] | vr[y];
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2: vr[x] <= vr[x] & vr[y];
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3: vr[x] <= vr[x] ^ vr[y];
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4: { vr[15], vr[x] } <= {8'b0, vr[x]} + {8'b0, vr[y]};
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5: begin
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vr[x] <= vr[x] - vr[y];
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vr[15] <= {7'b0, vr[x] >= vr[y]};
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end
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6: begin
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vr[15] <= {7'b0, vr[x][0]};
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vr[x] <= vr[x] >> 1;
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end
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7: begin
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vr[x] <= vr[y] - vr[x];
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vr[15] <= {7'b0, vr[y] >= vr[x]};
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end
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14: begin
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vr[15] <= {7'b0, vr[x][7]};
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vr[x] <= vr[x] << 1;
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end
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endcase
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end
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end
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endmodule
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