164 lines
5.7 KiB
Verilog
164 lines
5.7 KiB
Verilog
// Copyright (c) 2014 Sergiusz 'q3k' Bazański <sergiusz@bazanski.pl>
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// Licensed under 2-clause BSD - see COPYING file from software distribution
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`timescale 1ns / 1ps
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module core (
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input reset,
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input cpu_clock,
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input timer_clock,
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input [15:0] keypad
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);
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// 4k (12 bits) of 8-bit ram
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reg [7:0] ram[0:4095];
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// 16 8-bit V registers
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reg [7:0] v[0:15];
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// 16-bit I register
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reg [15:0] i;
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// 12-bit program counter
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reg [11:0] pc;
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// 8-bit stack pointer
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reg [7:0] sp;
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// internal cycle counter (0 - fetch)
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`define FETCH 0
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`define EXECUTE 1
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`define WRITEBACK 2
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reg [1:0] c;
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// Instruction register
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reg [15:0] ins;
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wire family = (ins >> 12);
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// ALU operation
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wire [3:0] alu_op = ins & 4'hF;
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// ALU source registers
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wire [3:0] alu_x = (ins >> 8) & 4'hF;
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wire [3:0] alu_y = (ins >> 4) & 4'hF;
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// ALU immediate
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wire [7:0] kk = ins & 8'hFF;
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wire [11:0] nnn = ins & 12'hFFF;
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// Jump register
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reg[15:0] jmp;
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// Should jump on FETCH?
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reg should_jmp;
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always @(cpu_clock)
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begin
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if (!reset) begin
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i <= 0;
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pc <= 0;
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sp <= 0;
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should_jmp <= 0;
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end else begin
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case(c)
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`FETCH: begin
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ins <= ram[pc] << 8 | ram[pc + 1];
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end
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`EXECUTE: begin
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case (family)
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// Jump to address
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1: begin
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should_jmp <= 1;
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jmp <= nnn;
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end
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// Call address
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2: begin
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should_jmp <= 1;
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ram[sp] <= pc;
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sp <= sp + 1;
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jmp <= nnn;
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end
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// Skip next if Vx == kk (3xkk)
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3: begin
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if (v[alu_x] == kk) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Skip next if Vx != kk (4xkk)
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4: begin
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if (v[alu_x] != kk) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Skip next if Vx == Vy (5xy0)
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5: begin
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if (v[alu_x] == v[alu_y]) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Vx <= kk
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6: v[alu_x] <= kk;
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// Vx += kk
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7: v[alu_x] <= v[alu_x] + kk;
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// ALU operation
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8: case(alu_op)
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0: v[alu_x] <= v[alu_y];
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1: v[alu_x] <= v[alu_x] | v[alu_y];
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2: v[alu_x] <= v[alu_x] & v[alu_y];
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3: v[alu_x] <= v[alu_x] ^ v[alu_y];
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4: { v[15], v[alu_x] } <= v[alu_x] + v[alu_y];
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5: { v[15], v[alu_x] } <= (v[alu_x] - v[alu_y]) ^ (1 << 8);
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6: begin
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v[15] <= v[alu_x][0];
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v[alu_x] <= v[alu_x] >> 1;
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end
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7: { v[15], v[alu_x] } <= (v[alu_y] - v[alu_x]) ^ (1 << 8);
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15: begin
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v[15] <= v[alu_x][7];
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v[alu_x] <= v[alu_x] << 1;
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end
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endcase
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// Skip if Vx != Vy (9xy0)
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9: begin
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if (v[alu_x] != v[alu_y]) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Set I to nnn
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10: i <= nnn;
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// Jump to nnn + V0
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11: begin
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should_jmp <= 1;
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jmp <= nnn + v[0];
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end
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// Set Vx to random and kk
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// TODO: undo fair dice roll
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12: v[alu_x] <= 42 & kk;
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// TODO: draw sprites
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13: begin end
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// Key functions
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14: begin
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if (kk == 8'h9E) begin
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if ((keypad >> alu_x) & 1) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end else if (kk == 8'hA1) begin
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if (((keypad >> alu_x) & 1) == 0) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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end
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endcase
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end
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`WRITEBACK: begin
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if (should_jmp) begin
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pc <= jmp;
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end else begin
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pc <= pc + 2;
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end
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should_jmp <= 0;
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end
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endcase
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end
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end
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endmodule
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