373 lines
14 KiB
Verilog
373 lines
14 KiB
Verilog
// Copyright (c) 2014 Sergiusz 'q3k' Bazański <sergiusz@bazanski.pl>
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// Licensed under 2-clause BSD - see COPYING file from software distribution
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`timescale 1ns / 1ps
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/* verilator lint_off UNDRIVEN */
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/* verilator lint_off UNUSED */
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/* verilator lint_off LITENDIAN */
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module cpu (
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input reset,
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input cpu_clock,
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input hertz_clock,
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input [15:0] keypad
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);
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// 4k (12 bits) of 8-bit ram
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reg [7:0] ram[0:4095]/* verilator public */;
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// 16 8-bit V registers
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reg [7:0] vr[0:15]/* verilator public */;
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// 16-bit I register
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reg [15:0] i/* verilator public */;
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// 12-bit memory-indexing version of I
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wire [11:0] ii = i[11:0];
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// 12-bit program counter
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reg [11:0] pc/* verilator public */;
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// 16-element, 12-bit stack
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reg [11:0] stack [0:15];
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// 4-bit stack pointer
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reg [3:0] sp;
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// 8-bit DT (delay timer)
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reg [7:0] dt/* verilator public */;
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// 8-bit ST (sound timer)
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reg [7:0] st;
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// internal cycle counter (0 - fetch)
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`define FETCH 0
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`define EXECUTE 1
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`define WRITEBACK 2
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`define WAIT_KEY 3
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reg [2:0] c/* verilator public */;
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// Instruction register
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reg [15:0] ins/* verilator public */;
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wire [3:0] family = ins[15:12];
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// ALU operation
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wire [3:0] alu_op = ins[3:0];
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wire is_alu_op = (c == `EXECUTE) && (family == 8);
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// Source register indexes
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wire [3:0] x = ins[11:8];
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wire [3:0] y = ins[7:4];
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// Immediates
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wire [7:0] kk = ins[7:0];
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wire [11:0] nnn = ins[11:0];
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// Jump register
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reg[11:0] jmp;
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// Should jump on FETCH?
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reg should_jmp;
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always @(posedge cpu_clock)
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begin
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if (!reset) begin
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i <= 0;
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pc <= 0;
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sp <= 0;
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should_jmp <= 0;
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c <= 0;
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dt <= 0;
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dt <= 0;
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vr[0] <= 0;
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vr[1] <= 0;
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vr[2] <= 0;
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vr[3] <= 0;
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vr[4] <= 0;
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vr[5] <= 0;
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vr[6] <= 0;
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vr[7] <= 0;
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vr[8] <= 0;
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vr[9] <= 0;
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vr[10] <= 0;
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vr[11] <= 0;
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vr[12] <= 0;
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vr[13] <= 0;
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vr[14] <= 0;
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vr[15] <= 0;
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end else begin
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case(c)
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`FETCH: begin
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ins <= {ram[pc], ram[pc + 1]};
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c <= 1;
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if (hertz_clock == 1) begin
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if (dt > 0)
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dt <= dt - 1;
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if (st > 0)
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st <= st - 1;
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end
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end
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`EXECUTE: begin
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// $display("TRACE %h @ %h", ins, pc);
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case (family)
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// Old native instructions - we implement them in
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// hardware
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0: begin
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if (ins == 16'h00E0) begin
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// clear screen
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$display("should clear, don't care.");
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end else if (ins == 16'h00EE) begin
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// return from subroutine
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jmp <= stack[sp-1];
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sp <= sp - 1;
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should_jmp <= 1;
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end else
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$display("Unknown opcode: %h @ %h", ins, pc);
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end
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// Jump to address
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1: begin
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should_jmp <= 1;
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jmp <= nnn;
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end
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// Call address
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2: begin
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should_jmp <= 1;
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stack[sp] <= pc;
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sp <= sp + 1;
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jmp <= nnn;
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end
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// Skip next if Vx == kk (3xkk)
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3: begin
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if (vr[x] == kk) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Skip next if Vx != kk (4xkk)
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4: begin
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if (vr[x] != kk) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Skip next if Vx == Vy (5xy0)
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5: begin
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if (vr[x] == vr[y]) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Vx <= kk
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6: vr[x] <= kk;
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// Vx += kk
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7: vr[x] <= vr[x] + kk;
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// These are implemented in the ALU
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8: begin end
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// Skip if Vx != Vy (9xy0)
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9: begin
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if (vr[x] != vr[y]) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end
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// Set I to nnn
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10: i <= {4'h0, nnn};
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// Jump to nnn + V0
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11: begin
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should_jmp <= 1;
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jmp <= nnn + {4'h0, vr[0]};
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end
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// Set Vx to random and kk
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// TODO: undo fair dice roll
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12: begin vr[x] <= 42 & kk; $display("STUB: random"); end
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// TODO: draw sprites
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13: begin end
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// Key functions
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14: begin
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if (kk == 8'h9E) begin
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if (keypad[x]) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end else if (kk == 8'hA1) begin
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if (~keypad[x]) begin
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should_jmp <= 1;
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jmp <= pc + 4;
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end
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end else $display("Unknown opcode: %h @ %h", ins, pc);
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end
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// Fxxx instructions (mostly timer related)
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15: begin
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case (kk)
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// load DT into Vx
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8'h07: vr[x] <= dt;
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// load Vx into DT
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8'h15: dt <= vr[x];
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// load Vx into ST
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8'h18: st <= vr[x];
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// add Vx to I
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8'h1E: begin i <= i + {8'b0, vr[x]}; $display("i, %h, vx %h", i, vr[x]); end
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// move Vx digit memory location to I
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8'h29: i <= 5 * vr[x];
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// store BCD rep of Vx into [I], [I+1], [I+2]
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8'h33: begin
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ram[ii+2] <= vr[x] / 100;
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ram[ii+1] <= (vr[x] / 10) % 10;
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ram[ii] <= vr[x] % 10;
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end
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// store V0 to Vx to [I], [I+1], ..., [I+x]
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8'h55: begin
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ram[ii] <= vr[0];
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if (x > 0) ram[ii+1] <= vr[1];
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if (x > 1) ram[ii+2] <= vr[2];
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if (x > 2) ram[ii+3] <= vr[3];
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if (x > 3) ram[ii+4] <= vr[4];
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if (x > 4) ram[ii+5] <= vr[5];
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if (x > 5) ram[ii+6] <= vr[6];
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if (x > 6) ram[ii+7] <= vr[7];
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if (x > 7) ram[ii+8] <= vr[8];
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if (x > 8) ram[ii+9] <= vr[9];
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if (x > 9) ram[ii+10] <= vr[10];
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if (x > 10) ram[ii+11] <= vr[11];
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if (x > 11) ram[ii+12] <= vr[12];
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if (x > 12) ram[ii+13] <= vr[13];
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if (x > 13) ram[ii+14] <= vr[14];
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if (x > 14) ram[ii+15] <= vr[15];
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end
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// read [I], [I+1], ..., [I+x] into V0 .. Vx
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8'h65: begin
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vr[0] <= ram[ii];
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if (x > 0) vr[1] <= ram[ii+1];
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if (x > 1) vr[1] <= ram[ii+2];
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if (x > 2) vr[1] <= ram[ii+3];
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if (x > 3) vr[1] <= ram[ii+4];
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if (x > 4) vr[1] <= ram[ii+5];
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if (x > 5) vr[1] <= ram[ii+6];
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if (x > 6) vr[1] <= ram[ii+7];
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if (x > 7) vr[1] <= ram[ii+8];
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if (x > 8) vr[1] <= ram[ii+9];
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if (x > 9) vr[1] <= ram[ii+10];
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if (x > 10) vr[1] <= ram[ii+11];
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if (x > 11) vr[1] <= ram[ii+12];
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if (x > 12) vr[1] <= ram[ii+13];
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if (x > 13) vr[1] <= ram[ii+14];
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if (x > 14) vr[1] <= ram[ii+15];
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end
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default: $display("Unknown opcode: %h @ %h", ins, pc);
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endcase
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end
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endcase
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if (family == 4'hF && kk == 8'h0A)
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c <= `WAIT_KEY;
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else
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c <= `WRITEBACK;
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end
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`WRITEBACK: begin
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if (should_jmp) begin
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pc <= jmp;
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end else begin
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pc <= pc + 2;
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end
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should_jmp <= 0;
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c <= 0;
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end
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`WAIT_KEY: begin
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$display("waiting for key");
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if (keypad != 0) begin
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case (keypad)
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16'h1: begin
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vr[x] <= 0;
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c <= `WRITEBACK;
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end
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16'h2: begin
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vr[x] <= 1;
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c <= `WRITEBACK;
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end
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16'h4: begin
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vr[x] <= 2;
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c <= `WRITEBACK;
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end
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16'h8: begin
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vr[x] <= 3;
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c <= `WRITEBACK;
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end
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16'h10: begin
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vr[x] <= 4;
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c <= `WRITEBACK;
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end
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16'h20: begin
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vr[x] <= 5;
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c <= `WRITEBACK;
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end
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16'h40: begin
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vr[x] <= 6;
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c <= `WRITEBACK;
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end
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16'h80: begin
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vr[x] <= 7;
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c <= `WRITEBACK;
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end
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16'h100: begin
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vr[x] <= 8;
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c <= `WRITEBACK;
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end
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16'h200: begin
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vr[x] <= 9;
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c <= `WRITEBACK;
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end
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16'h400: begin
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vr[x] <= 10;
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c <= `WRITEBACK;
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end
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16'h800: begin
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vr[x] <= 11;
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c <= `WRITEBACK;
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end
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16'h1000: begin
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vr[x] <= 12;
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c <= `WRITEBACK;
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end
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16'h2000: begin
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vr[x] <= 13;
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c <= `WRITEBACK;
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end
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16'h4000: begin
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vr[x] <= 14;
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c <= `WRITEBACK;
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end
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16'h8000: begin
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vr[x] <= 15;
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c <= `WRITEBACK;
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end
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endcase
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end
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end
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endcase
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end
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end
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// ALU
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always @(posedge cpu_clock)
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begin
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if (is_alu_op) begin
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case(alu_op)
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0: vr[x] <= vr[y];
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1: vr[x] <= vr[x] | vr[y];
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2: vr[x] <= vr[x] & vr[y];
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3: vr[x] <= vr[x] ^ vr[y];
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4: { vr[15], vr[x] } <= {8'b0, vr[x]} + {8'b0, vr[y]};
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5: begin
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vr[x] <= vr[x] - vr[y];
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vr[15] <= {7'b0, vr[x] >= vr[y]};
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end
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6: begin
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vr[15] <= {7'b0, vr[x][0]};
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vr[x] <= vr[x] >> 1;
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end
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7: begin
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vr[x] <= vr[y] - vr[x];
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vr[15] <= {7'b0, vr[y] >= vr[x]};
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end
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14: begin
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vr[15] <= {7'b0, vr[x][7]};
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vr[x] <= vr[x] << 1;
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end
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default: $display("Unknown opcode: %h @ %h", ins, pc);
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endcase
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end
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end
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endmodule
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