52 lines
869 B
Verilog
52 lines
869 B
Verilog
module qm_top(
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);
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// Fetch / Decode
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reg [31:0] FD_IR;
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reg [31:0] FD_NextPC;
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// Decode / Execute
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reg [31:0] DE_A;
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reg [31:0] DE_B;
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reg [31:0] DE_Imm;
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reg [31:0] DE_IR;
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wire [31:0] ICache_Address;
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wire [31:0] ICache_Data;
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wire ICache_Hit;
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wire ICache_ShouldStall;
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// ICache
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qm_icache icache(
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.reset(reset),
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.clk(sys_clk),
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.address(ICache_Address),
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.data(ICache_Data),
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.hit(ICache_Hit),
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.stall(ICache_ShouldStall),
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.enable(ICache_Enable)
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);
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// Fetch
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wire [31:0] fetch_IR;
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wire [31:0] fetch_NextPC;
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qm_fetch fetch(
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.di_PC(FD_NextPC),
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.do_IR(fetch_IR),
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.do_NextPC(fetch_NextPC),
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.icache_address(ICache_Address),
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.icache_hit(ICache_Hit),
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.icache_should_stall(ICache_ShouldStall),
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.icache_data(ICache_Data)
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);
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always @(posedge clk) begin
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FD_IR <= fetch_IR;
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FD_NextPC <= fetch_NextPC;
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end
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endmodule
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