27 lines
488 B
Verilog
27 lines
488 B
Verilog
module qm_regfile(
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input wire we3,
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input wire [4:0] ra1,
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input wire [4:0] ra2,
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input wire [4:0] wa3,
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output wire [31:0] rd1,
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output wire [31:0] rd2,
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input wire [31:0] wd3
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);
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// three ported register file
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// two read ports, one write port
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// actual flops
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reg [31:0] rf [31:0];
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always @(wd3) begin
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if (we3 && wa != 0) begin
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rf[wa3] = wd3;
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end
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end
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assign rd1 = (ra1 == 0 ? 0 : rf[ra1]);
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assign rd2 = (ra2 == 0 ? 0 : rf[ra2]);
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endmodule
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