30 lines
630 B
Verilog
30 lines
630 B
Verilog
module qm_fetch(
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/// datapath
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// input PC to assume
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input wire [31:0] di_PC,
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// output instruction register
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output wire [31:0] do_IR,
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// output to next PC
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output wire [31:0] do_NextPC,
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// icache connectivity
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output wire [31:0] icache_address,
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input wire icache_hit,
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input wire icache_should_stall,
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input wire [31:0] icache_data
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);
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assign icache_address = di_PC;
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always @(*) begin
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if (icache_should_stall && !icache_hit) begin
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do_NextPC = di_PC;
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do_IR = 0;
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end else begin
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do_NextPC = di_PC + 4;
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do_IR = icache_data;
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end
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end
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endmodule
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