132 lines
4.2 KiB
Verilog
132 lines
4.2 KiB
Verilog
`define OP_SPECIAL 6'b000000
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`define OP_SPECIAL2 6'b011100
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`define OP_ADDI 6'b001000 // addi rt, rs, imm ; rt = rs + imm
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`define OP_ADDIU 6'b001001 // addiu rt, rs, imm ; rt = rs + imm
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`define OP_ANDI 6'b001100 // andi rt, rs, imm ; rt = rs & imm
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`define OP_ORI 6'b001101
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`define OP_XORI 6'b001110
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`define OP_SLTI 6'b001010
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`define OP_SLTIU 6'b001011
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`define OP_LB 6'b100000
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`define OP_LH 6'b100001
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`define OP_LBU 6'b100100
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`define OP_LHU 6'b100101
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`define OP_LW 6'b100011 // lw rt, imm(rs) ; rt = [rs+imm]
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`define OP_SW 6'b101011 // sw rt, imm(rs) ; [rs + imm] = rt
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// Special 0
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`define FUNCT_ADD 6'b100000
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`define FUNCT_ADDU 6'b100001
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`define FUNCT_AND 6'b100100
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`define FUNCT_DIV 6'b011010
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`define FUNCT_DIVU 6'b011011
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`define FUNCT_MULT 6'b011000
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`define FUNCT_MULTU 6'b011001
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`define FUNCT_NOR 6'b100111
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`define FUNCT_OR 6'b100101
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`define FUNCT_SLT 6'b101010
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`define FUNCT_SUB 6'b100010
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`define FUNCT_SUBU 6'b100011
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`define FUNCT_XOR 6'b100110
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// Special 2
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//`define FUNCT_CLO 6'b100001
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//`define FUNCT_CLZ 6'b100000
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//`define FUNCT_MADD 6'b000000
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//`define FUNCT_MADDU 6'b000001
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//`define FUNCT_MSUB 6'b000100
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//`define FUNCT_MSUBU 6'b000101
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//`define FUNCT_MUL 6'b000010
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`include "defines.v"
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module qm_control(
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/// Instruction from the decode stage
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input wire [5:0] opcode,
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input wire [5:0] funct,
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/// Control lines to the pipeline stages
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// Mux selecting the destination register for the register writeback
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// 0 - RT
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// 1 - RD
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output wire reg_destination,
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// Mux selecting the source of the ALU B operand
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// 0 - Value of RT register
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// 1 - instruction Imediate part
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output wire alu_source,
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// ALU Control signal, select ALU operation
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output wire [3:0] alu_control,
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// Memory write enable signal
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output wire mem_write,
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// Mux selecting the source of the data for the register writeback
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// 0 - output of ALU
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// 1 - data read from memory
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output wire reg_wsource,
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// Register writeback enable signal
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output wire reg_write
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);
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always @(opcode, funct) begin
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case (opcode)
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`OP_SPECIAL: begin
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reg_destination <= 1;
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alu_source <= 0;
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mem_write <= 0;
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reg_wsource <= 0;
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reg_write <= 1;
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case (funct)
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`FUNCT_ADD: <= `ALU_ADD;
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`FUNCT_ADDU: <= `ALU_ADD;
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`FUNCT_AND: <= `ALU_AND;
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`FUNCT_DIV: <= `ALU_DIV;
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`FUNCT_DIVU: <= `ALU_DIV;
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`FUNCT_MULT: <= `ALU_MUL;
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`FUNCT_MULTU: <= `ALU_MUL;
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`FUNCT_NOR: <= `ALU_NOR
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`FUNCT_OR: <= `ALU_OR;
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`FUNCT_SLT: <= `ALU_SLT;
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`FUNCT_SUB: <= `ALU_SUB;
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`FUNCT_SUBU: <= `ALU_SUB;
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`FUNCT_XOR: <= `ALU_XOR;
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endcase
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end
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`OP_LW: begin
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reg_destination <= 0;
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alu_source <= 1;
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alu_control <= 0;
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mem_write <= 0;
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reg_wsource <= 1;
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reg_write <= 1;
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end
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`OP_SW: begin
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reg_destination <= 0;
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alu_source <= 1;
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alu_control <= 0;
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mem_write <= 1;
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reg_wsource <= 0;
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reg_write <= 0;
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end
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6'b001???: // all immediate arith/logic
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default: begin
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reg_destination <= 0;
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alu_source <= 0;
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mem_write <= 0;
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reg_wsource <= 0;
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reg_write <= 0;
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case (opcode)
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`OP_ADDI: alu_control <= `ALU_ADD;
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`OP_ADDIU: alu_control <= `ALU_ADD;
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`OP_ANDI: alu_control <= `ALU_AND;
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`OP_ORI: alu_control <= `ALU_OR;
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`OP_XORI: alu_control <= `ALU_XOR;
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`OP_SLTI: alu_control <= `ALU_SLT;
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`OP_SLTIU: alu_control <= `ALU_SLTIU;
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endcase
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end
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endcase
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end
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endmodule
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