53 lines
2.1 KiB
Verilog
53 lines
2.1 KiB
Verilog
// Copyright (c) 2014, Segiusz 'q3k' Bazanski <sergiusz@bazanski.pl>
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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`include "defines.v"
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// Right now this ALU doesn't do any sort of overflow traps - mathematicians
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// beware!
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module qm_alu(
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input wire [3:0] i_ALUControl,
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input wire [31:0] i_A,
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input wire [31:0] i_B,
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output reg [31:0] o_Result,
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always @(i_ALUControl, i_A, i_B) begin
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case (i_ALUControl)
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`ALU_ADD: o_Result = i_A + i_B;
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`ALU_AND: o_Result = i_A & i_B;
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`ALU_OR: o_Result = i_A | i_B;
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`ALU_XOR: o_Result = i_A ^ i_B;
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`ALU_SLT: o_Result = i_A << i_B;
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`ALU_SUB: o_Result = i_A - i_B;
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`ALU_DIV: o_Result = i_A / i_B;
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`ALU_MUL: o_Result = i_A * i_B;
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`ALU_NOR: o_Result = ~(i_A | i_B);
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endcase
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end
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);
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endmodule
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