156 lines
5.1 KiB
C++
156 lines
5.1 KiB
C++
// Copyright (c) 2014, Segiusz 'q3k' Bazanski <sergiusz@bazanski.pl>
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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#include "test_icache.h"
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#include <cstdio>
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#include "Vqm_icache.h"
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unsigned int _read_ram_at(unsigned int address)
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{
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// for now, just return the address
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return address;
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}
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void simulate_memory_controller(Vqm_icache *ic)
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{
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static unsigned int latched_cmd_instr;
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static unsigned int latched_cmd_bl;
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static unsigned int latched_cmd_addr;
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static int previous_cmd_clock = 0;
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static int previous_rd_clock = 0;
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//printf("[mem ctrl] clk %i, ci 0x%01x, cb %i, ca %08x, ce %i\n",
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// ic->mem_cmd_clk, ic->mem_cmd_instr, ic->mem_cmd_bl, ic->mem_cmd_addr, ic->mem_cmd_en);
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static struct {
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int instr = -1;
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unsigned int left = 0;
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unsigned int addr = 0;
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} current_command;
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if (previous_cmd_clock == 0 && ic->mem_cmd_clk == 1)
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{
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// simulate rising edge of command clock
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if (ic->mem_cmd_en)
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{
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printf("[mem ctrl] got command 0x%01x with bi %i and addres %08x\n",
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latched_cmd_instr, latched_cmd_bl, latched_cmd_addr);
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current_command.instr = latched_cmd_instr;
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current_command.left = latched_cmd_bl + 1;
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current_command.addr = latched_cmd_addr;
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ic->mem_cmd_empty = 0;
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}
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latched_cmd_instr = ic->mem_cmd_instr;
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latched_cmd_bl = ic->mem_cmd_bl;
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latched_cmd_addr = ic->mem_cmd_addr;
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}
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if (previous_rd_clock == 0 && ic->mem_cmd_clk == 1)
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{
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// simulate read
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if (ic->mem_rd_en)
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{
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if (current_command.instr == 0x01)
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{
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if (current_command.left == 0)
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{
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current_command.instr = -1;
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ic->mem_rd_empty = 1;
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printf("[mem ctrl] command end\n");
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}
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else
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{
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printf("[mem ctrl] command word, %i left\n", current_command.left-1);
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ic->mem_rd_data = _read_ram_at(current_command.addr + (4-current_command.left)*4);
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ic->mem_rd_empty = 0;
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current_command.left--;
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}
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}
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}
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}
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previous_cmd_clock = ic->mem_cmd_clk;
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previous_rd_clock = ic->mem_rd_clk;
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}
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void test_icache(void)
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{
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Vqm_icache *icache = new Vqm_icache;
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icache->mem_cmd_full = 0;
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icache->mem_cmd_empty = 1;
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icache->mem_rd_full = 0;
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icache->mem_rd_empty = 1;
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icache->mem_rd_count = 0;
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icache->address = 0;
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icache->enable = 0;
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// reset
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icache->reset = 1;
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icache->clk = 0;
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icache->eval();
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icache->clk = 1;
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icache->eval();
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icache->reset = 0;
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icache->clk = 0;
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icache->eval();
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icache->clk = 1;
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icache->eval();
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icache->clk = 0;
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icache->eval();
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unsigned int counter = 0;
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while (1)
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{
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if (counter == 10)
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{
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printf("[TEST] Trying to read from 0x8bedead0...\n");
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icache->enable = 1;
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icache->address = 0x8bedead0;
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}
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if (counter > 11 && icache->stall == 0 && icache->address != 0x8bedead4)
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{
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printf("[TEST] Trying to read from 0x8bedead4 (should take one cycle...)\n");
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icache->address = 0x8bedead4;
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}
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if (counter > 40 && icache->stall == 0 && icache->address != 0x8bedead8)
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{
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printf("[TEST] Trying to read from 0x8bedead8 (should take one cycle...)\n");
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icache->address = 0x8bedead8;
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}
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if (counter > 100)
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break;
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icache->clk = !icache->clk;
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icache->eval();
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printf("[cache input] a: %08x\n", icache->address);
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printf("[cache status] hit: %i, stall: %i, data %08x\n",
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icache->hit, icache->stall, icache->data);
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simulate_memory_controller(icache);
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counter++;
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}
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}
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