179 lines
4.7 KiB
Verilog
179 lines
4.7 KiB
Verilog
// Copyright (c) 2014, Segiusz 'q3k' Bazanski <sergiusz@bazanski.pl>
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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`include "qm_control.v"
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`include "qm_icache.v"
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`include "qm_fetch.v"
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`include "qm_decode.v"
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module qm_top(
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input wire clk
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);
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/// Controlpath signal inputs
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// Decode/Execute
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reg DEC_RegWrite;
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reg DEC_RegWSource;
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reg DEC_MemWrite;
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reg [3:0] DEC_ALUControl;
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reg DEC_ALUSource;
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reg DEC_RegDest;
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/// Controlpath signal outputs
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wire cdecode_RegWrite;
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wire cdecode_RegWSource;
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wire cdecode_MemWrite;
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wire [3:0] cdecode_ALUControl;
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wire cdecode_ALUSource;
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wire cdecode_RegDest;
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/// Datapath signal inputs
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// Fetch / Decode
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reg [31:0] FD_IR;
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reg [31:0] FD_NextPC;
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// Decode / Execute
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reg [31:0] DE_RSVal;
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reg [31:0] DE_RTVal;
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reg [31:0] DE_Imm;
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reg [31:0] DE_RT;
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reg [31:0] DE_RD;
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/// Datapath signal outputs
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// Fetch
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wire [31:0] fetch_IR;
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wire [31:0] fetch_NextPC;
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// Decode
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wire [31:0] decode_RSVal;
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wire [31:0] decode_RTVal;
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wire [31:0] decode_Imm;
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wire [4:0] decode_RT;
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wire [4:0] decode_RD;
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wire [5:0] decode_Opcode;
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wire [5:0] decode_Function;
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// ICache
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wire [31:0] ICache_Address;
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wire [31:0] ICache_Data;
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wire ICache_Hit;
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wire ICache_ShouldStall;
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/// Pipeline step
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always @(posedge clk) begin
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// Fetch -> Decode
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FD_IR <= fetch_IR;
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FD_NextPC <= fetch_NextPC;
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// Decode -> Execute
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DE_RSVal <= decode_RSVal;
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DE_RTVal <= decode_RTVal;
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DE_Imm <= decode_Imm;
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DE_RT <= decode_RT;
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DE_RD <= decode_RD;
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DEC_RegWrite <= cdecode_RegWrite;
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DEC_RegWSource <= cdecode_RegWSource;
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DEC_MemWrite <= cdecode_MemWrite;
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DEC_ALUControl <= cdecode_ALUControl;
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DEC_ALUSource <= cdecode_ALUSource;
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DEC_RegDest <= cdecode_RegDest;
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end
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/// Impelementations
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// Control unit
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// Extra internal signals, to Decode...
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wire control_RegDest;
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wire control_ALUSource;
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wire [3:0] control_ALUControl;
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wire control_MemWrite;
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wire control_RegWSource;
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wire control_RegWrite;
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wire control_Branch;
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qm_control control(
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.i_Opcode(decode_Opcode),
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.i_Function(decode_Function),
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.co_RegDest(control_RegDest),
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.co_ALUSource(control_ALUSource),
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.co_ALUControl(control_ALUControl),
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.co_MemWrite(control_MemWrite),
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.co_RegWSource(control_RegWSource),
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.co_RegWrite(control_RegWrite),
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.co_Branch(control_Branch)
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);
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// ICache
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qm_icache icache(
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.reset(reset),
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.clk(sys_clk),
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.address(ICache_Address),
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.data(ICache_Data),
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.hit(ICache_Hit),
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.stall(ICache_ShouldStall),
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.enable(ICache_Enable)
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);
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//Fetch
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qm_fetch fetch(
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.di_PC(FD_NextPC),
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.do_IR(fetch_IR),
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.do_NextPC(fetch_NextPC),
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.icache_address(ICache_Address),
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.icache_hit(ICache_Hit),
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.icache_should_stall(ICache_ShouldStall),
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.icache_data(ICache_Data)
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);
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// Decode
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qm_decode decode(
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.di_IR(fetch_IR),
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.do_RSVal(decode_RSVal),
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.do_RTVal(decode_RTVal),
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.do_Imm(decode_Imm),
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.do_RT(decode_RT),
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.do_RD(decode_RD),
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.di_WA(0),
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.di_WE(0),
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.di_WD(0),
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.o_Opcode(decode_Opcode),
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.o_Function(decode_Function),
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.ci_RegWrite(control_RegWrite),
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.ci_RegWSource(control_RegWSource),
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.ci_MemWrite(control_MemWrite),
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.ci_ALUControl(control_ALUControl),
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.ci_ALUSource(control_ALUSource),
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.ci_RegDest(control_RegDest),
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.co_RegDest(cdecode_RegDest),
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.co_ALUSource(cdecode_ALUSource),
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.co_ALUControl(cdecode_ALUControl),
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.co_MemWrite(cdecode_MemWrite),
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.co_RegWSource(cdecode_RegWSource),
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.co_RegWrite(cdecode_RegWrite)
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);
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endmodule
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