77 lines
2.4 KiB
Verilog
77 lines
2.4 KiB
Verilog
// Copyright (c) 2014, Segiusz 'q3k' Bazanski <sergiusz@bazanski.pl>
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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`include "qm_alu.v"
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module qm_execute(
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/// datapath
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// from Decode
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input wire [31:0] di_RSVal,
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input wire [31:0] di_RTVal,
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input wire [31:0] di_Imm,
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input wire [4:0] di_RT,
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input wire [4:0] di_RD,
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// to Memory
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output wire [31:0] do_ALUOut,
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output wire [31:0] do_WriteData,
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output wire [31:0] do_WriteReg,
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/// controlpath
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// from Decode
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input wire ci_RegWrite,
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input wire ci_RegWSource,
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input wire ci_MemWrite,
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input wire [3:0] ci_ALUControl,
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input wire ci_ALUSource,
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input wire ci_RegDest
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// to Memory
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output wire co_RegWrite,
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output wire co_RegWSource,
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output wire co_MemWrite
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);
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// passthrough
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assign co_RegWrite = ci_RegWrite;
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assign co_RegWSource = ci_RegWSource;
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assign co_MemWrite = ci_MemWrite;
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assign do_WriteData = di_RTVal;
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// Mux to ALU B
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wire ALUB = ci_ALUSource ? di_RTVal : di_Imm;
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// Mux to register write index
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assign do_WriteReg = ci_RegDest ? di_RT : di_RD;
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qm_alu alu(
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.i_ALUControl(ci_ALUControl),
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.i_A(di_RSVal),
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.i_B(ALUB),
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.o_Result(do_ALUOut)
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);
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endmodule
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