100 lines
3.0 KiB
Verilog
100 lines
3.0 KiB
Verilog
// Copyright (c) 2014, Segiusz 'q3k' Bazanski <sergiusz@bazanski.pl>
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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`include "qm_regfile.v"
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/* verilator lint_off UNUSED */
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module qm_decode(
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/// datapath
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// from Fetch
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input wire [31:0] di_IR,
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// backtraced from decode
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input wire [4:0] di_WA,
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input wire di_WE,
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input wire [31:0] di_WD,
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output wire [31:0] do_RSVal,
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output wire [31:0] do_RTVal,
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output wire [31:0] do_Imm,
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output wire [4:0] do_RT,
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output wire [4:0] do_RD,
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/// instruction to control unit
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output wire [5:0] o_Opcode,
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output wire [5:0] o_Function,
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/// controlpath
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input wire ci_RegWrite,
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input wire ci_RegWSource,
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input wire ci_MemWrite,
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input wire [3:0] ci_ALUControl,
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input wire ci_ALUSource,
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input wire ci_RegDest,
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input wire ci_Branch,
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output wire co_RegWrite,
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output wire co_RegWSource,
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output wire co_MemWrite,
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output wire [3:0] co_ALUControl,
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output wire co_ALUSource,
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output wire co_RegDest
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);
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// passthrough
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assign co_RegWrite = ci_RegWrite;
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assign co_RegWSource = ci_RegWSource;
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assign co_MemWrite = ci_MemWrite;
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assign co_ALUControl = ci_ALUControl;
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assign co_ALUSource = ci_ALUSource;
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assign co_RegDest = ci_RegDest;
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// internal signals from the IR
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wire [4:0] rs;
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wire [4:0] rt;
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wire [15:0] imm;
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assign rs = di_IR[25:21];
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assign rt = di_IR[20:16];
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assign imm = di_IR[15:0];
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qm_regfile regfile(
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.ra1(rs),
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.ra2(rt),
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.rd1(do_RSVal),
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.rd2(do_RTVal),
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.wa3(di_WA),
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.we3(di_WE),
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.wd3(di_WD)
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);
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// sign extend imm
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assign do_Imm[31:0] = { {16{imm[15]}}, imm[15:0] };
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assign do_RT = rt;
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assign do_RD = di_IR[15:11];
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assign o_Opcode = di_IR[31:26];
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assign o_Function = di_IR[5:0];
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endmodule
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