Add execute pipeline step.

Signed-off-by: Sergiusz 'q3k' Bazański <q3k@q3k.org>

rtl/verilog/qm_alu.v

@@ -0,0 +1,51 @@
+// Copyright (c) 2014, Segiusz 'q3k' Bazanski <sergiusz@bazanski.pl>
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+//
+// 1. Redistributions of source code must retain the above copyright notice,
+//    this list of conditions and the following disclaimer.
+// 2. Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+
+`include "defines.v"
+
+// Right now this ALU doesn't do any sort of overflow traps - mathematicians
+// beware!
+module qm_alu(
+    input wire [3:0] i_ALUControl,
+    input wire [31:0] i_A,
+    input wire [31:0] i_B,
+
+    output reg [31:0] o_Result,
+
+    always @(i_ALUControl, i_A, i_B) begin
+        case (i_ALUControl)
+            `ALU_ADD: o_Result = i_A + i_B;
+            `ALU_AND: o_Result = i_A & i_B;
+            `ALU_OR:  o_Result = i_A | i_B;
+            `ALU_XOR: o_Result = i_A ^ i_B;
+            `ALU_SLT: o_Result = i_A << i_B;
+            `ALU_SUB: o_Result = i_A - i_B;
+            `ALU_DIV: o_Result = i_A / i_B;
+            `ALU_MUL: o_Result = i_A * i_B;
+            `ALU_NOR: o_Result = ~(i_A | i_B);
+        endcase
+    end
+);
+
+endmodule

rtl/verilog/qm_decode.v

@@ -37,8 +37,8 @@ module qm_decode(
     output wire [31:0] do_RSVal,
     output wire [31:0] do_RTVal,
     output wire [31:0] do_Imm,
-    output wire [4:0] do_RS,
     output wire [4:0] do_RT,
+    output wire [4:0] do_RD,
 
     /// instruction to control unit
     output wire [5:0] o_Opcode,
@@ -90,9 +90,8 @@ qm_regfile regfile(
 
 // sign extend imm
 assign do_Imm[31:0] = { {16{imm[15]}}, imm[15:0] };
-assign do_RS = rs;
 assign do_RT = rt;
-
+assign do_RD = di_IR[15:11];
 assign o_Opcode = di_IR[31:26];
 assign o_Function = di_IR[5:0];
 

rtl/verilog/qm_execute.v

@@ -0,0 +1,75 @@
+// Copyright (c) 2014, Segiusz 'q3k' Bazanski <sergiusz@bazanski.pl>
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+//
+// 1. Redistributions of source code must retain the above copyright notice,
+//    this list of conditions and the following disclaimer.
+// 2. Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+
+`include "qm_alu.v"
+
+module qm_execute(
+    /// datapath
+    // from Decode
+    input wire [31:0] di_RSVal,
+    input wire [31:0] di_RTVal,
+    input wire [31:0] di_Imm,
+    input wire [4:0] di_RT,
+    input wire [4:0] di_RD,
+    // to Memory
+    output wire [31:0] do_ALUOut,
+    output wire [31:0] do_WriteData,
+    output wire [31:0] do_WriteReg,
+
+    /// controlpath
+    // from Decode
+    input wire ci_RegWrite,
+    input wire ci_RegWSource,
+    input wire ci_MemWrite,
+    input wire [3:0] ci_ALUControl,
+    input wire ci_ALUSource,
+    input wire ci_RegDest
+    // to Memory
+    output wire co_RegWrite,
+    output wire co_RegWSource,
+    output wire co_MemWrite
+);
+
+// passthrough
+assign co_RegWrite = ci_RegWrite;
+assign co_RegWSource = ci_RegWSource;
+assign co_MemWrite = ci_MemWrite;
+
+assign do_WriteData = di_RTVal;
+
+// Mux to ALU B
+wire ALUB = ci_ALUSource ? di_RTVal : di_Imm;
+
+// Mux to register write index
+assign do_WriteReg = ci_RegDest ? di_RT : di_RD;
+
+qm_alu alu(
+    .i_ALUControl(ci_ALUControl),
+    .i_A(di_RSVal),
+    .i_B(ALUB),
+
+    .o_Result(do_ALUOut)
+);
+
+endmodule

rtl/verilog/qm_top.v

@@ -56,8 +56,8 @@ reg [31:0] FD_NextPC;
 reg [31:0] DE_RSVal;
 reg [31:0] DE_RTVal;
 reg [31:0] DE_Imm;
-reg [31:0] DE_RS;
 reg [31:0] DE_RT;
+reg [31:0] DE_RD;
 
 /// Datapath signal outputs
 // Fetch
@@ -67,8 +67,8 @@ wire [31:0] fetch_NextPC;
 wire [31:0] decode_RSVal;
 wire [31:0] decode_RTVal;
 wire [31:0] decode_Imm;
-wire [4:0] decode_RS;
 wire [4:0] decode_RT;
+wire [4:0] decode_RD;
 wire [5:0] decode_Opcode;
 wire [5:0] decode_Function;
 // ICache
@@ -87,8 +87,8 @@ always @(posedge clk) begin
     DE_RSVal <= decode_RSVal;
     DE_RTVal <= decode_RTVal;
     DE_Imm <= decode_Imm;
-    DE_RS <= decode_RS;
     DE_RT <= decode_RT;
+    DE_RD <= decode_RD;
 
     DEC_RegWrite <= cdecode_RegWrite;
     DEC_RegWSource <= cdecode_RegWSource;
@@ -149,8 +149,8 @@ qm_decode decode(
     .do_RSVal(decode_RSVal),
     .do_RTVal(decode_RTVal),
     .do_Imm(decode_Imm),
-    .do_RS(decode_RS),
     .do_RT(decode_RT),
+    .do_RD(decode_RD),
 
     .di_WA(0),
     .di_WE(0),