First memory backend in icache
parent
1797089f79
commit
97d85b2f77
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@ -1,11 +1,29 @@
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/* verilator lint_off UNUSED */
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module qm_icache(
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input wire [31:0] address,
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input wire reset,
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input wire clk,
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// to the consumer (CPU fetch stage)
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output wire hit,
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output wire stall,
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output wire [31:0] data
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output wire [31:0] data,
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// to the memory controller (no wishbone yet...)
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output wire mem_cmd_clk, // we will keep this synchronous to the input clock
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output wire mem_cmd_en,
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output wire [2:0] mem_cmd_instr,
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output wire [5:0] mem_cmd_bl,
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output wire [29:0] mem_cmd_addr,
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input wire mem_cmd_full,
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input wire mem_cmd_empty,
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output wire mem_rd_clk,
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output wire mem_rd_en,
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input wire [6:0] mem_rd_count,
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input wire mem_rd_full,
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input wire [31:0] mem_rd_data,
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input wire mem_rd_empty
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);
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@ -28,6 +46,8 @@ assign index_tag = lines[index][143:128];
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assign address_tag = address[31:16];
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assign address_word = address[3:2];
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assign mem_rd_clk = clk;
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assign mem_cmd_clk = clk;
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// reset condition
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generate
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@ -40,9 +60,16 @@ generate
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end
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end
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endgenerate
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always @(posedge clk)
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if (reset)
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always @(posedge clk) begin
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if (reset) begin
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valid_bit <= 1;
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memory_read_state <= 0;
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mem_cmd_en <= 0;
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mem_cmd_bl <= 0;
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mem_cmd_instr <= 0;
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mem_rd_en <= 0;
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end
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end
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// read condition
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always @(address) begin
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@ -63,4 +90,57 @@ always @(address) begin
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end
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end
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// if we are stalling, it means that our consumer is waiting for us to
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// read memory and provide it data
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reg [2:0] memory_read_state;
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always @(posedge clk) begin
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if (stall && !reset) begin
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case (memory_read_state)
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0: begin // assert command
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mem_cmd_instr <= 1; // read
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mem_cmd_bl <= 4; // four words
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mem_cmd_addr <= address[29:0]; // from the address we are being asserted
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mem_cmd_en <= 0;
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memory_read_state <= 1;
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end
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1: begin // assert enable
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mem_cmd_en <= 1;
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memory_read_state <= 2;
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mem_rd_en <= 1;
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end
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2: begin // wait for first word
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mem_cmd_en <= 0;
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if (!mem_rd_empty) begin
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lines[index][31:0] <= mem_rd_data;
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memory_read_state <= 3;
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end
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end
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3: begin // wait for second word
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if (!mem_rd_empty) begin
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lines[index][63:32] <= mem_rd_data;
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memory_read_state <= 4;
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end
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end
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4: begin // wait for third word
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if (!mem_rd_empty) begin
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lines[index][95:64] <= mem_rd_data;
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memory_read_state <= 5;
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end
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end
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5: begin // wait for fourth word
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if (!mem_rd_empty) begin
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lines[index][127:96] <= mem_rd_data;
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memory_read_state <= 0;
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mem_rd_en <= 0;
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// write tag
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lines[index][143:128] <= address_tag;
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// and valid bit - our cominatorial logic will now turn
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// off stalling and indicate a hit to the consumer
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lines[index][144] <= valid_bit;
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end
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end
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endcase
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end
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end
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endmodule
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