Commit graph

145352 commits

Author SHA1 Message Date
Kevin Hilman
b0958aed1e [ARM] 5529/1: davinci: MMC platform support: DMA_32BIT_MASK --> DMA_BIT_MASK(32)
Some DMA_32BIT_MASK usage snuck in with the MMC platform support.
Convert these to the new preferred DMA_BIT_MASK(32).

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-05-29 19:59:13 +01:00
Russell King
42f1d2e06a Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci into devel 2009-05-29 10:04:24 +01:00
Kevin Hilman
77bbca138c davinci: defconfig update: add EMAC
DaVinci EMAC driver is now upstream.  Enable it in default defconfig.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 15:29:37 -07:00
David Brownell
20e9969b3a davinci: add SRAM allocator
Provide a generic SRAM allocator using genalloc, and vaguely
modeled after what AVR32 uses.  This builds on top of the
static CPU mapping set up in the previous patch, and returns
DMA mappings as requested (if possible).

Compared to its OMAP cousin, there's no current support for
(currently non-existent) DaVinci power management code running
in SRAM; and this has ways to deallocate, instead of being
allocate-only.

The initial user of this should probably be the audio code,
because EDMA from DDR is subject to various dropouts on at
least DM355 and DM6446 chips.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 15:18:13 -07:00
David Brownell
0d04eb4705 davinci: soc-specific SRAM setup
Package on-chip SRAM.  It's always accessible from the ARM, so
set up a standardized virtual address mapping into a 128 KiB
area that's reserved for platform use.

In some cases (dm6467) the physical addresses used for EDMA are
not the same as the ones used by the ARM ... so record that info
separately in the SOC data, for chips (unlike the OMAP-L137)
where SRAM may be used with EDMA.

Other blocks of SRAM, such as the ETB buffer or DSP L1/L2 RAM,
may be unused/available on some system.  They are ignored here.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 15:18:12 -07:00
David Brownell
b79dbdefd2 davinci: remove remnants of IRAM allocator
Remove remnants of dm6446-specific SRAM allocator, as preparation for
a more generic replacement.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 15:18:12 -07:00
Kevin Hilman
96ed299fdb davinci: cleanup: move dm355 UART2 define to dm355.c
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 15:17:49 -07:00
Mark A. Greer
5570078c0e davinci: Move PINMUX defines to SoC files
Different SoC have different numbers of pinmux registers and other
resources that overlap with each other.  To clean up the code and
eliminate defines that overlap with each other, move the PINMUX
defines to the SoC specific files.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 15:17:48 -07:00
Mark A. Greer
3abd5acfff davinci: Add compare register support to timer code
The Timer64p timer has 8 compare registers that can
be used to generate interrupts when the timer value
matches the compare reg's value.  They do not disturb
the timer itself.  This can be useful when there is
only one timer available for both clock events and
clocksource.

When enabled, the clocksource remains a continuous
32-bit counter but the clock event will no longer
support periodic interrupts.  Instead only oneshot
timers will be supported and implemented by setting
the compare register to the current timer value plus
the period that the clock event subsystem is requesting.

Compare registers support is enabled automatically
when the following conditions are met:
1) The same timer is being used for clock events
   and clocksource.
2) The timer is the bottom half (32 bits) of the
   64-bit timer (hardware limitation).
3) The the compare register offset and irq are
   not zero.

Since the timer is always running, there is a hardware
race in timer32_config() between reading the current
timer value, and adding the period to the current
timer value and writing the compare register.
Testing on a da830 evm board with the timer clocked
at 24 MHz and the processor clocked at 300 MHz,
showed the number of counter ticks to do this ranged
from 20-53 (~1-2.2 usecs) but usually around 41 ticks.
This includes some artifacts from collecting the
information.  So, the minimum period should be
at least 5 usecs to be safe.

There is also an non-critical lower limit that
the period should be since there is no point in
setting an event that is much shorter than the
time it takes to set the event, and get & handle
the timer interrupt for that event.  There can
also be all sorts of delays from activities
occuring elsewhere in the system (including
hardware activitis like cache & TLB management).
These are virtually impossible to quantify so a
minimum period of 50 usecs was chosen.  That will
certianly be enough to avoid the actual hardware
race but hopefully not large enough to cause
unreasonably course-grained timers.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 15:17:48 -07:00
Mark A. Greer
0b0c4c2a69 davinci: Integrate cp_intc support into low-level irq code
Integrate the Common Platform Interrupt Controller (cp_intc)
support into the low-level irq handling for davinci and similar
platforms.  Do it such that support for cp_intc and the original
aintc can coexist in the same kernel binary.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 15:17:47 -07:00
Mark A. Greer
b14dc0f994 davinci: Factor out emac mac address handling
Factor out the code to extract that mac address from
i2c eeprom.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 15:17:47 -07:00
Mark A. Greer
c97909fcf1 davinci: Remove unused i2c eeprom_read/write routines
The dm644x and dm646x board files have i2c eeprom read and
write routines but they are not used so remove them.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 15:17:46 -07:00
Mark A. Greer
972412b648 davinci: Move emac platform_data to SoC-specific files
Since most of the emac platform_data is really SoC specific
and not board specific, move it to the SoC-specific files.
Put a pointer to the platform_data in the soc_info structure
so the board-specific code can set some of the platform_data
if it needs to.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 15:17:45 -07:00
Mark A. Greer
65e866a974 davinci: Move serial platform_device into SoC-specific files
Currently, there is one set of platform_device and platform_data
structures for all DaVinci SoCs.  The differences in the data
between the various SoCs is handled by davinci_serial_init()
by checking the SoC type.  However, as new SoCs appear, this
routine will become more & more cluttered.

To clean up the routine and make it easier to add support for new
SoCs, move the platform_device and platform_data structures into the
SoC-specific code and use the SoC infrastructure to provide access
to the data.

In the process, fix a bug where the wrong irq is used for uart2
of the dm646x.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 15:17:41 -07:00
Mark A. Greer
a994955cc0 davinci: Make GPIO code more generic
The current gpio code needs to know the number of
gpio irqs there are and what the bank irq number is.
To determine those values, it checks the SoC type.

It also assumes that the base address and the number
of irqs the interrupt controller uses is fixed.

To clean up the SoC checks and make it support
different base addresses and interrupt controllers,
have the SoC-specific code set those values in
the soc_info structure and have the gpio code
reference them there.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 15:16:30 -07:00
Mark A. Greer
951d6f6d70 davinci: Add watchdog base address flexibility
The watchdog code currently hardcodes the base address
of the timer its using.  To support new SoCs, make it
support timers at any address.  Use the soc_info structure
to do this.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 08:20:31 -07:00
Mark A. Greer
f64691b3ab davinci: Add base address and timer flexibility
The davinci timer code currently hardcodes the timer register
base addresses, the timer irq numbers, and the timers to use
for clock events and clocksource.  This won't work for some
a new SoC so put those values into the soc_info structure
and set them up in the SoC-specific files.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 08:19:04 -07:00
Mark A. Greer
673dd36f0d davinci: Move interrupt ctlr info to SoC infrastructure
Use the SoC infrastructure to hold the interrupt controller
information (i.e., base address, default priorities,
interrupt controller type, and the number of IRQs).

The interrupt controller base, although initially put
in the soc_info structure's intc_base field, is eventually
put in the global 'davinci_intc_base' so the low-level
interrupt code can access it without a dereference.

These changes enable the SoC default irq priorities to be
put in the SoC-specific files, and the interrupt controller
to be at any base address.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 08:18:09 -07:00
Mark A. Greer
0e585952ac davinci: Move pinmux setup info to SoC infrastructure
The pinmux register base and setup can be different for different
SoCs so move the pinmux reg base, pinmux table (and its size) to
the SoC infrastructure.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 08:17:16 -07:00
Mark A. Greer
d81d188caf davinci: Add support for multiple PSCs
The current code to support the DaVinci Power and Sleep Controller (PSC)
assumes that there is only one controller.  This assumption is no longer
valid so expand the support to allow greater than one PSC.

To accomplish this, put the base addresses for the PSCs in the SoC
infrastructure so it can be referenced by the PSC code.  This also
requires adding an extra parameter to davinci_psc_config() to specify
the PSC that is to be enabled/disabled.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 08:16:46 -07:00
Mark A. Greer
66e0c3991c davinci: Add clock init call to common init routine
All of the davinci SoCs need to call davinci_clk_init() so
put the call in the common init routine.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 08:14:59 -07:00
Mark A. Greer
b9ab12797e davinci: Support JTAG ID register at any address
The Davinci cpu_is_davinci_*() macros use the SoC part number
and variant retrieved from the JTAG ID register to determine the
type of cpu that the kernel is running on.  Currently, the code to
read the JTAG ID register assumes that the register is always at
the same base address.  This isn't true on some newer SoCs.

To solve this, have the SoC-specific code set the JTAG ID register
base address in soc_info structure and add a 'cpu_id' member to it.
'cpu_id' will be used by the cpu_is_davinci_*() macros to match
the cpu id.  Also move the info used to identify the cpu type into
the SoC-specific code to keep all SoC-specific code together.

The common code will read the JTAG ID register, search through
an array of davinci_id structures to identify the cpu type.
Once identified, it will set the 'cpu_id' member of the soc_info
structure to the proper value and the cpu_is_davinci_*() macros
will now work.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 08:14:56 -07:00
Mark A. Greer
79c3c0b729 davinci: Encapsulate SoC-specific data in a structure
Create a structure to encapsulate SoC-specific information.
This will assist in generalizing code so it can be used by
different SoCs that have similar hardware but with minor
differences such as having a different base address.

The idea is that the code for each SoC fills out a structure
with the correct information.  The board-specific code then
calls the SoC init routine which in turn will call a common
init routine that makes a copy of the structure, maps in I/O
regions, etc.

After initialization, code can get a pointer to the structure
by calling davinci_get_soc_info().  Eventually, the common
init routine will make a copy of all of the data pointed to
by the structure so the original data can be made __init_data.
That way the data for SoC's that aren't being used won't consume
memory for the entire life of the kernel.

The structure will be extended in subsequent patches but
initially, it holds the map_desc structure for any I/O
regions the SoC/board wants statically mapped.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 08:14:04 -07:00
Kevin Hilman
ac7b75b5bb davinci: EMAC platform support
Add SoC and platform-specific data and init for DaVinci EMAC network
driver.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 07:18:16 -07:00
Kevin Hilman
2dbf56aeb7 davinci: MMC platform support
Add SoC and platform-specific data and init for MMC driver.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 07:18:16 -07:00
Kevin Hilman
35652fe185 davinci: update davinci_all_defconfig for dm355, dm6467
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 07:18:15 -07:00
Kevin Hilman
e38d92fdcd davinci: DM646x: add base SoC and board support
Add support for DM646x SoC (a.k.a DaVinci HD) and its Evalution
Module (EVM.)

Original support done by Sudhakar Rajashekhara.

Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 07:18:15 -07:00
Kevin Hilman
95a3477fe5 davinci: DM355: add base SoC and board support
In addition, add board support for the DM355 Evaluation Module (EVM)
and the DM355 Leopard board.

Original DM355 EVM support done by Sandeep Paulraj, with significant
updates and improvements by David Brownell.  DM355 Leopord support
done by Koen Kooi.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Koen Kooi <koen@beagleboard.org>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 07:18:15 -07:00
Hugo Villeneuve
f5ce6a67a7 davinci: DM644x: add support for SFFSDR board
Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 07:18:15 -07:00
Kevin Hilman
fb6313879c davinci: add platform support for watchdog timer
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 07:18:15 -07:00
Sergei Shtylyov
0521444d49 davinci: INTC: add support for TI cp_intc
Add support for Texas Instuments Common Platform Interrupt Controller
(cp_intc) used on DA830/OMAP-L137.

Signed-off-by: Steve Chen <schen@mvista.com>
Signed-off-by: Mark Greer <mgreer@mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 07:18:14 -07:00
Mark A. Greer
27428e39da davinci: support different UART bases for zImage uncompress
The davinci pre-kernel boot code assumes that all platforms use the
same UART base address for the console.  That assumption is not longer
valid with some newer SoCs so determine the console UART base address
from the machine number passed in from bootloader.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 07:18:14 -07:00
Troy Kisky
ce8ccaf0ef davinci: interrupts: get_irqnr_and_base: save an instruction
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 07:18:14 -07:00
Chaithrika U S
17eb157041 davinci: use 32-bit accesses for low-level debug macros
This patch defines debug macros for low-level debugging for Davinci
based platforms

Tested on :
        - DM644x DaVinci EVM
        - DM646X DaVinciHD EVM
	- DM355 EVM

This patch attempts to solve the low-level debug issue in DM646x. The
UART on DM646x SoC allows only 32-bit access. The existing
debug-macro.S uses the macros from debug-8250.S file. This led to
garbage serial out in the case of DM646x.

The inclusion of debug-8250.S does not allow for run time fix for this
issue.  There are compile time errors due to multiple definitions of
the macros.  Also when building a single image for multiple DaVinci
Platforms, the ifdefs cannot be relied upon.

The solution below does not include the debug-8250.S file and defines
the necessary macros. This solution was arrived at after observing
that word access does not affect the low-level debug messages on
DM644x/DM355.

The other approach to this issue is to use the UART module information
available in the peripheral registers to decide the access
mechanism. But this will have to be done for every access of UART
specifically for DM646x. Also this calls for a modification of the
debug-8250.S file.

Signed-off-by: Chaithrika U S <chaithrika@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 07:18:14 -07:00
Kevin Hilman
dc75602628 davinci: fixups for banked GPIO interrupt handling
This patch seems to get me much more reliable performance using the
GPIO banked interrupts on dm355 for the dm9000 driver.

Changes include:

- init GPIO handling along with normal GPIO init
- mask the level-sensitive bank IRQ during handling

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 07:17:54 -07:00
David Brownell
df4aab46a8 davinci: gpio irq enable tweaks
Fix two IRQ triggering bugs affecting GPIO IRQs:

 - Make sure enabling with IRQ_TYPE_NONE ("default, unspecified")
   isn't a NOP ... default to both edges, at least one must work.

 - As noted by Kevin Hilman, setting the irq trigger type for a
   banked gpio interrupt shouldn't enable irqs that are disabled.

Since GPIO IRQs haven't been used much yet, it's not clear these
bugs could have affected anything.  The few current users don't
seem to have been obviously suffering from these issues.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-26 07:17:54 -07:00
Russell King
9af5324a07 Merge branch 'ixp4xx' of git://git.kernel.org/pub/scm/linux/kernel/git/chris/linux-2.6 into devel 2009-05-25 13:35:46 +01:00
Krzysztof Hałasa
9733bb8e9c IXP4xx: Change QMgr function names to qmgr_stat_*_watermark and clean the comments.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
2009-05-25 13:25:34 +02:00
Russell King
56a459314a Merge branch 'iommu' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git into devel 2009-05-25 10:20:21 +01:00
Russell King
fc05505b77 Merge branch 'ixp4xx' of git://git.kernel.org/pub/scm/linux/kernel/git/chris/linux-2.6 into devel 2009-05-23 23:18:40 +01:00
Krzysztof Hałasa
11c79740d3 IXP4xx: support for Goramo MultiLink router platform.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
2009-05-23 23:58:30 +02:00
Linus Torvalds
59a3759d0f Linux 2.6.30-rc7 2009-05-23 14:47:00 -07:00
Krzysztof Hałasa
0771c69394 IXP42x: Use __fls() in QMgr interrupt handlers.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
2009-05-23 23:37:04 +02:00
Krzysztof Hałasa
d4c9e9fc97 IXP42x: Add QMgr support for IXP425 rev. A0 processors.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
2009-05-23 23:36:03 +02:00
Krzysztof Hałasa
61a5ccc85a IXP42x: add NPE support for IXP425 rev. A0 processors.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
2009-05-23 23:16:23 +02:00
Krzysztof Hałasa
8a4fe82497 IXP42x: Identify Intel IXP425 rev. A0 processors.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
2009-05-23 23:16:21 +02:00
Krzysztof Hałasa
2e41840072 IXP4xx: Whitespace fixes in the Ethernet driver.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
2009-05-23 23:14:59 +02:00
Krzysztof Hałasa
6a68afe3a2 IXP4xx: Ethernet and WAN drivers now support "high" hardware queues.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
2009-05-23 23:14:10 +02:00
Linus Torvalds
4a5daceca1 Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-rc-fixes-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-rc-fixes-2.6:
  [SCSI] mpt2sas: fix driver version inconsistency
  [SCSI] 3w-xxxx: scsi_dma_unmap fix
  [SCSI] 3w-9xxx: scsi_dma_unmap fix
  [SCSI] ses: fix problems caused by empty SES provided name
  [SCSI] fc-transport: Close state transition-window during rport deletion.
  [SCSI] initialize max_target_blocked in scsi_alloc_target
  [SCSI] fnic: Add new Cisco PCI-Express FCoE HBA
2009-05-23 13:44:00 -07:00
Linus Torvalds
3eb9c8be0c Merge git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6:
  [CIFS] Avoid open on possible directories since Samba now rejects them
2009-05-23 13:42:53 -07:00