2005-04-16 22:20:36 +00:00
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/* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
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* irq.c: UltraSparc IRQ handling/init/registry.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
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* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/ptrace.h>
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#include <linux/errno.h>
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#include <linux/kernel_stat.h>
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#include <linux/signal.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/proc_fs.h>
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#include <linux/seq_file.h>
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2006-02-12 07:07:13 +00:00
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#include <linux/bootmem.h>
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2006-06-20 08:23:32 +00:00
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#include <linux/irq.h>
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[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 01:41:02 +00:00
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#include <linux/msi.h>
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2005-04-16 22:20:36 +00:00
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/atomic.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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2005-10-09 04:12:04 +00:00
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#include <asm/io.h>
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2005-04-16 22:20:36 +00:00
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#include <asm/sbus.h>
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#include <asm/iommu.h>
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#include <asm/upa.h>
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#include <asm/oplib.h>
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2006-06-23 03:21:22 +00:00
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#include <asm/prom.h>
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2005-04-16 22:20:36 +00:00
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#include <asm/timer.h>
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#include <asm/smp.h>
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#include <asm/starfire.h>
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#include <asm/uaccess.h>
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#include <asm/cache.h>
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#include <asm/cpudata.h>
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2005-06-28 00:04:45 +00:00
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#include <asm/auxio.h>
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2006-02-27 07:27:19 +00:00
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#include <asm/head.h>
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2005-04-16 22:20:36 +00:00
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/* UPA nodes send interrupt packet to UltraSparc with first data reg
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* value low 5 (7 on Starfire) bits holding the IRQ identifier being
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* delivered. We must translate this into a non-vector IRQ so we can
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* set the softint on this cpu.
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*
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* To make processing these packets efficient and race free we use
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* an array of irq buckets below. The interrupt vector handler in
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* entry.S feeds incoming packets into per-cpu pil-indexed lists.
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* The IVEC handler does not need to act atomically, the PIL dispatch
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* code uses CAS to get an atomic snapshot of the list and clear it
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* at the same time.
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2006-06-20 08:23:32 +00:00
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*
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* If you make changes to ino_bucket, please update hand coded assembler
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* of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
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2005-04-16 22:20:36 +00:00
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*/
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2006-06-20 08:23:32 +00:00
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struct ino_bucket {
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/* Next handler in per-CPU IRQ worklist. We know that
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* bucket pointers have the high 32-bits clear, so to
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* save space we only store the bits we need.
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*/
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/*0x00*/unsigned int irq_chain;
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2005-04-16 22:20:36 +00:00
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2006-06-20 08:23:32 +00:00
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/* Virtual interrupt number assigned to this INO. */
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/*0x04*/unsigned int virt_irq;
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};
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#define NUM_IVECS (IMAP_INR + 1)
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2005-04-16 22:20:36 +00:00
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struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
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2006-06-20 08:23:32 +00:00
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#define __irq_ino(irq) \
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(((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
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#define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
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#define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
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2005-04-16 22:20:36 +00:00
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/* This has to be in the main kernel image, it cannot be
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* turned into per-cpu data. The reason is that the main
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* kernel image is locked into the TLB and this structure
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* is accessed from the vectored interrupt trap handler. If
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* access to this structure takes a TLB miss it could cause
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* the 5-level sparc v9 trap stack to overflow.
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*/
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2006-06-20 08:20:00 +00:00
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#define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist)
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2005-04-16 22:20:36 +00:00
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2006-06-20 08:22:35 +00:00
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static unsigned int virt_to_real_irq_table[NR_IRQS];
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static unsigned char virt_irq_alloc(unsigned int real_irq)
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{
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unsigned char ent;
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BUILD_BUG_ON(NR_IRQS >= 256);
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[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 01:41:02 +00:00
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for (ent = 1; ent < NR_IRQS; ent++) {
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if (!virt_to_real_irq_table[ent])
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break;
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}
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2006-06-20 08:22:35 +00:00
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if (ent >= NR_IRQS) {
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printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
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return 0;
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}
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virt_to_real_irq_table[ent] = real_irq;
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return ent;
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}
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|
|
[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 01:41:02 +00:00
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static void virt_irq_free(unsigned int virt_irq)
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2006-06-20 08:22:35 +00:00
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{
|
[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 01:41:02 +00:00
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unsigned int real_irq;
|
2006-06-20 08:22:35 +00:00
|
|
|
|
[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 01:41:02 +00:00
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if (virt_irq >= NR_IRQS)
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return;
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real_irq = virt_to_real_irq_table[virt_irq];
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virt_to_real_irq_table[virt_irq] = 0;
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__bucket(real_irq)->virt_irq = 0;
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2006-06-20 08:22:35 +00:00
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}
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static unsigned int virt_to_real_irq(unsigned char virt_irq)
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{
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return virt_to_real_irq_table[virt_irq];
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}
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2005-04-16 22:20:36 +00:00
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/*
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2006-06-20 08:23:32 +00:00
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* /proc/interrupts printing:
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2005-04-16 22:20:36 +00:00
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*/
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int show_interrupts(struct seq_file *p, void *v)
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{
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2006-06-20 08:23:32 +00:00
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int i = *(loff_t *) v, j;
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struct irqaction * action;
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2005-04-16 22:20:36 +00:00
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unsigned long flags;
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2006-06-20 08:23:32 +00:00
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if (i == 0) {
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seq_printf(p, " ");
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for_each_online_cpu(j)
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seq_printf(p, "CPU%d ",j);
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seq_putc(p, '\n');
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}
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if (i < NR_IRQS) {
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spin_lock_irqsave(&irq_desc[i].lock, flags);
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action = irq_desc[i].action;
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if (!action)
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goto skip;
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seq_printf(p, "%3d: ",i);
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2005-04-16 22:20:36 +00:00
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#ifndef CONFIG_SMP
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seq_printf(p, "%10u ", kstat_irqs(i));
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#else
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2006-06-20 08:23:32 +00:00
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
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2005-04-16 22:20:36 +00:00
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#endif
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[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 09:24:36 +00:00
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seq_printf(p, " %9s", irq_desc[i].chip->typename);
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2006-06-20 08:23:32 +00:00
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seq_printf(p, " %s", action->name);
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for (action=action->next; action; action = action->next)
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2006-06-20 08:21:57 +00:00
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seq_printf(p, ", %s", action->name);
|
2006-06-20 08:23:32 +00:00
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|
2005-04-16 22:20:36 +00:00
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seq_putc(p, '\n');
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2006-06-20 08:23:32 +00:00
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skip:
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spin_unlock_irqrestore(&irq_desc[i].lock, flags);
|
2005-04-16 22:20:36 +00:00
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}
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return 0;
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}
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|
2006-02-17 16:38:06 +00:00
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extern unsigned long real_hard_smp_processor_id(void);
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static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
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{
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unsigned int tid;
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if (this_is_starfire) {
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tid = starfire_translate(imap, cpuid);
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tid <<= IMAP_TID_SHIFT;
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tid &= IMAP_TID_UPA;
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} else {
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if (tlb_type == cheetah || tlb_type == cheetah_plus) {
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unsigned long ver;
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__asm__ ("rdpr %%ver, %0" : "=r" (ver));
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if ((ver >> 32UL) == __JALAPENO_ID ||
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(ver >> 32UL) == __SERRANO_ID) {
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tid = cpuid << IMAP_TID_SHIFT;
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|
|
|
|
tid &= IMAP_TID_JBUS;
|
|
|
|
|
} else {
|
|
|
|
|
unsigned int a = cpuid & 0x1f;
|
|
|
|
|
unsigned int n = (cpuid >> 5) & 0x1f;
|
|
|
|
|
|
|
|
|
|
tid = ((a << IMAP_AID_SHIFT) |
|
|
|
|
|
(n << IMAP_NID_SHIFT));
|
|
|
|
|
tid &= (IMAP_AID_SAFARI |
|
|
|
|
|
IMAP_NID_SAFARI);;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
tid = cpuid << IMAP_TID_SHIFT;
|
|
|
|
|
tid &= IMAP_TID_UPA;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return tid;
|
|
|
|
|
}
|
|
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
struct irq_handler_data {
|
|
|
|
|
unsigned long iclr;
|
|
|
|
|
unsigned long imap;
|
2006-06-20 08:22:35 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
void (*pre_handler)(unsigned int, void *, void *);
|
|
|
|
|
void *pre_handler_arg1;
|
|
|
|
|
void *pre_handler_arg2;
|
|
|
|
|
};
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
static inline struct ino_bucket *virt_irq_to_bucket(unsigned int virt_irq)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2006-06-20 08:22:35 +00:00
|
|
|
unsigned int real_irq = virt_to_real_irq(virt_irq);
|
2006-06-20 08:23:32 +00:00
|
|
|
struct ino_bucket *bucket = NULL;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
if (likely(real_irq))
|
|
|
|
|
bucket = __bucket(real_irq);
|
2006-06-20 08:22:35 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
return bucket;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
static int irq_choose_cpu(unsigned int virt_irq)
|
2005-07-04 20:24:38 +00:00
|
|
|
{
|
2006-06-29 09:24:38 +00:00
|
|
|
cpumask_t mask = irq_desc[virt_irq].affinity;
|
2006-06-20 08:23:32 +00:00
|
|
|
int cpuid;
|
2005-07-04 20:24:38 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
if (cpus_equal(mask, CPU_MASK_ALL)) {
|
|
|
|
|
static int irq_rover;
|
|
|
|
|
static DEFINE_SPINLOCK(irq_rover_lock);
|
|
|
|
|
unsigned long flags;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
/* Round-robin distribution... */
|
|
|
|
|
do_round_robin:
|
|
|
|
|
spin_lock_irqsave(&irq_rover_lock, flags);
|
2006-02-14 02:22:57 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
while (!cpu_online(irq_rover)) {
|
|
|
|
|
if (++irq_rover >= NR_CPUS)
|
|
|
|
|
irq_rover = 0;
|
|
|
|
|
}
|
|
|
|
|
cpuid = irq_rover;
|
|
|
|
|
do {
|
|
|
|
|
if (++irq_rover >= NR_CPUS)
|
|
|
|
|
irq_rover = 0;
|
|
|
|
|
} while (!cpu_online(irq_rover));
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
spin_unlock_irqrestore(&irq_rover_lock, flags);
|
|
|
|
|
} else {
|
|
|
|
|
cpumask_t tmp;
|
2005-07-04 20:24:38 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
cpus_and(tmp, cpu_online_map, mask);
|
2005-07-04 20:24:38 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
if (cpus_empty(tmp))
|
|
|
|
|
goto do_round_robin;
|
2005-07-04 20:24:38 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
cpuid = first_cpu(tmp);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2005-07-04 20:24:38 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
return cpuid;
|
|
|
|
|
}
|
|
|
|
|
#else
|
|
|
|
|
static int irq_choose_cpu(unsigned int virt_irq)
|
|
|
|
|
{
|
|
|
|
|
return real_hard_smp_processor_id();
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2006-06-20 08:23:32 +00:00
|
|
|
#endif
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
static void sun4u_irq_enable(unsigned int virt_irq)
|
2006-02-14 02:16:10 +00:00
|
|
|
{
|
2007-01-29 20:12:28 +00:00
|
|
|
struct irq_handler_data *data = get_irq_chip_data(virt_irq);
|
2006-02-14 02:16:10 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
if (likely(data)) {
|
|
|
|
|
unsigned long cpuid, imap;
|
|
|
|
|
unsigned int tid;
|
2006-02-14 02:16:10 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
cpuid = irq_choose_cpu(virt_irq);
|
|
|
|
|
imap = data->imap;
|
2006-02-14 02:16:10 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
tid = sun4u_compute_tid(imap, cpuid);
|
2006-02-14 02:16:10 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
upa_writel(tid | IMAP_VALID, imap);
|
2006-02-14 02:16:10 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
static void sun4u_irq_disable(unsigned int virt_irq)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2007-01-29 20:12:28 +00:00
|
|
|
struct irq_handler_data *data = get_irq_chip_data(virt_irq);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
if (likely(data)) {
|
|
|
|
|
unsigned long imap = data->imap;
|
|
|
|
|
u32 tmp = upa_readl(imap);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
tmp &= ~IMAP_VALID;
|
|
|
|
|
upa_writel(tmp, imap);
|
2005-07-04 20:24:38 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
static void sun4u_irq_end(unsigned int virt_irq)
|
2005-07-04 20:24:38 +00:00
|
|
|
{
|
2007-01-29 20:12:28 +00:00
|
|
|
struct irq_handler_data *data = get_irq_chip_data(virt_irq);
|
2005-07-04 20:24:38 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
if (likely(data))
|
|
|
|
|
upa_writel(ICLR_IDLE, data->iclr);
|
2005-07-04 20:24:38 +00:00
|
|
|
}
|
|
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
static void sun4v_irq_enable(unsigned int virt_irq)
|
2005-07-04 20:24:38 +00:00
|
|
|
{
|
2006-06-20 08:23:32 +00:00
|
|
|
struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
|
|
|
|
|
unsigned int ino = bucket - &ivector_table[0];
|
2005-07-04 20:24:38 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
if (likely(bucket)) {
|
|
|
|
|
unsigned long cpuid;
|
|
|
|
|
int err;
|
2005-07-04 20:24:38 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
cpuid = irq_choose_cpu(virt_irq);
|
2005-07-04 20:24:38 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
err = sun4v_intr_settarget(ino, cpuid);
|
|
|
|
|
if (err != HV_EOK)
|
|
|
|
|
printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
|
|
|
|
|
ino, cpuid, err);
|
|
|
|
|
err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
|
|
|
|
|
if (err != HV_EOK)
|
|
|
|
|
printk("sun4v_intr_setenabled(%x): err(%d)\n",
|
|
|
|
|
ino, err);
|
2005-07-04 20:24:38 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
static void sun4v_irq_disable(unsigned int virt_irq)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2006-06-20 08:23:32 +00:00
|
|
|
struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
|
|
|
|
|
unsigned int ino = bucket - &ivector_table[0];
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
if (likely(bucket)) {
|
|
|
|
|
int err;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
|
|
|
|
|
if (err != HV_EOK)
|
|
|
|
|
printk("sun4v_intr_setenabled(%x): "
|
|
|
|
|
"err(%d)\n", ino, err);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2006-06-20 08:23:32 +00:00
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
|
[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 01:41:02 +00:00
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
|
|
|
static void sun4v_msi_enable(unsigned int virt_irq)
|
|
|
|
|
{
|
|
|
|
|
sun4v_irq_enable(virt_irq);
|
|
|
|
|
unmask_msi_irq(virt_irq);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void sun4v_msi_disable(unsigned int virt_irq)
|
|
|
|
|
{
|
|
|
|
|
mask_msi_irq(virt_irq);
|
|
|
|
|
sun4v_irq_disable(virt_irq);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
static void sun4v_irq_end(unsigned int virt_irq)
|
|
|
|
|
{
|
|
|
|
|
struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
|
|
|
|
|
unsigned int ino = bucket - &ivector_table[0];
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
if (likely(bucket)) {
|
|
|
|
|
int err;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
|
|
|
|
|
if (err != HV_EOK)
|
|
|
|
|
printk("sun4v_intr_setstate(%x): "
|
|
|
|
|
"err(%d)\n", ino, err);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
static void run_pre_handler(unsigned int virt_irq)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2006-06-20 08:23:32 +00:00
|
|
|
struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
|
2007-01-29 20:12:28 +00:00
|
|
|
struct irq_handler_data *data = get_irq_chip_data(virt_irq);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
if (likely(data->pre_handler)) {
|
|
|
|
|
data->pre_handler(__irq_ino(__irq(bucket)),
|
|
|
|
|
data->pre_handler_arg1,
|
|
|
|
|
data->pre_handler_arg2);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2005-07-04 20:24:38 +00:00
|
|
|
}
|
|
|
|
|
|
2006-12-12 08:59:12 +00:00
|
|
|
static struct irq_chip sun4u_irq = {
|
2006-06-20 08:23:32 +00:00
|
|
|
.typename = "sun4u",
|
|
|
|
|
.enable = sun4u_irq_enable,
|
|
|
|
|
.disable = sun4u_irq_disable,
|
|
|
|
|
.end = sun4u_irq_end,
|
|
|
|
|
};
|
2006-06-20 08:22:35 +00:00
|
|
|
|
2006-12-12 08:59:12 +00:00
|
|
|
static struct irq_chip sun4u_irq_ack = {
|
2006-06-20 08:23:32 +00:00
|
|
|
.typename = "sun4u+ack",
|
|
|
|
|
.enable = sun4u_irq_enable,
|
|
|
|
|
.disable = sun4u_irq_disable,
|
|
|
|
|
.ack = run_pre_handler,
|
|
|
|
|
.end = sun4u_irq_end,
|
|
|
|
|
};
|
2005-07-04 20:24:38 +00:00
|
|
|
|
2006-12-12 08:59:12 +00:00
|
|
|
static struct irq_chip sun4v_irq = {
|
2006-06-20 08:23:32 +00:00
|
|
|
.typename = "sun4v",
|
|
|
|
|
.enable = sun4v_irq_enable,
|
|
|
|
|
.disable = sun4v_irq_disable,
|
|
|
|
|
.end = sun4v_irq_end,
|
|
|
|
|
};
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-12-12 08:59:12 +00:00
|
|
|
static struct irq_chip sun4v_irq_ack = {
|
2006-06-20 08:23:32 +00:00
|
|
|
.typename = "sun4v+ack",
|
|
|
|
|
.enable = sun4v_irq_enable,
|
|
|
|
|
.disable = sun4v_irq_disable,
|
|
|
|
|
.ack = run_pre_handler,
|
|
|
|
|
.end = sun4v_irq_end,
|
|
|
|
|
};
|
2005-04-16 22:20:36 +00:00
|
|
|
|
[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 01:41:02 +00:00
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
|
|
|
static struct irq_chip sun4v_msi = {
|
|
|
|
|
.typename = "sun4v+msi",
|
|
|
|
|
.mask = mask_msi_irq,
|
|
|
|
|
.unmask = unmask_msi_irq,
|
|
|
|
|
.enable = sun4v_msi_enable,
|
|
|
|
|
.disable = sun4v_msi_disable,
|
|
|
|
|
.ack = run_pre_handler,
|
|
|
|
|
.end = sun4v_irq_end,
|
|
|
|
|
};
|
|
|
|
|
#endif
|
|
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
void irq_install_pre_handler(int virt_irq,
|
|
|
|
|
void (*func)(unsigned int, void *, void *),
|
|
|
|
|
void *arg1, void *arg2)
|
|
|
|
|
{
|
2007-01-29 20:12:28 +00:00
|
|
|
struct irq_handler_data *data = get_irq_chip_data(virt_irq);
|
|
|
|
|
struct irq_chip *chip;
|
2005-07-04 20:24:38 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
data->pre_handler = func;
|
|
|
|
|
data->pre_handler_arg1 = arg1;
|
|
|
|
|
data->pre_handler_arg2 = arg2;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2007-01-29 20:12:28 +00:00
|
|
|
chip = get_irq_chip(virt_irq);
|
|
|
|
|
if (chip == &sun4u_irq_ack ||
|
[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 01:41:02 +00:00
|
|
|
chip == &sun4v_irq_ack
|
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
|
|
|
|| chip == &sun4v_msi
|
|
|
|
|
#endif
|
|
|
|
|
)
|
2006-06-29 21:38:21 +00:00
|
|
|
return;
|
|
|
|
|
|
2007-01-29 20:12:28 +00:00
|
|
|
chip = (chip == &sun4u_irq ?
|
|
|
|
|
&sun4u_irq_ack : &sun4v_irq_ack);
|
|
|
|
|
set_irq_chip(virt_irq, chip);
|
2006-06-20 08:23:32 +00:00
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
|
|
|
|
|
{
|
|
|
|
|
struct ino_bucket *bucket;
|
|
|
|
|
struct irq_handler_data *data;
|
|
|
|
|
int ino;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
BUG_ON(tlb_type == hypervisor);
|
2005-07-04 20:24:38 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
|
|
|
|
|
bucket = &ivector_table[ino];
|
|
|
|
|
if (!bucket->virt_irq) {
|
|
|
|
|
bucket->virt_irq = virt_irq_alloc(__irq(bucket));
|
2007-01-29 20:12:28 +00:00
|
|
|
set_irq_chip(bucket->virt_irq, &sun4u_irq);
|
2006-06-20 08:20:00 +00:00
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2007-01-29 20:12:28 +00:00
|
|
|
data = get_irq_chip_data(bucket->virt_irq);
|
|
|
|
|
if (unlikely(data))
|
2006-06-20 08:23:32 +00:00
|
|
|
goto out;
|
2006-06-20 08:20:00 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
|
|
|
|
|
if (unlikely(!data)) {
|
|
|
|
|
prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
|
|
|
|
|
prom_halt();
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2007-01-29 20:12:28 +00:00
|
|
|
set_irq_chip_data(bucket->virt_irq, data);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
data->imap = imap;
|
|
|
|
|
data->iclr = iclr;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
out:
|
|
|
|
|
return bucket->virt_irq;
|
|
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2006-06-20 08:22:35 +00:00
|
|
|
struct ino_bucket *bucket;
|
2006-06-20 08:23:32 +00:00
|
|
|
struct irq_handler_data *data;
|
|
|
|
|
unsigned long sysino;
|
2006-06-20 08:22:35 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
BUG_ON(tlb_type != hypervisor);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
sysino = sun4v_devino_to_sysino(devhandle, devino);
|
|
|
|
|
bucket = &ivector_table[sysino];
|
|
|
|
|
if (!bucket->virt_irq) {
|
|
|
|
|
bucket->virt_irq = virt_irq_alloc(__irq(bucket));
|
2007-01-29 20:12:28 +00:00
|
|
|
set_irq_chip(bucket->virt_irq, &sun4v_irq);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
2007-01-29 20:12:28 +00:00
|
|
|
data = get_irq_chip_data(bucket->virt_irq);
|
|
|
|
|
if (unlikely(data))
|
2005-04-16 22:20:36 +00:00
|
|
|
goto out;
|
|
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
|
|
|
|
|
if (unlikely(!data)) {
|
|
|
|
|
prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
|
|
|
|
|
prom_halt();
|
|
|
|
|
}
|
2007-01-29 20:12:28 +00:00
|
|
|
set_irq_chip_data(bucket->virt_irq, data);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
/* Catch accidental accesses to these things. IMAP/ICLR handling
|
|
|
|
|
* is done by hypervisor calls on sun4v platforms, not by direct
|
|
|
|
|
* register accesses.
|
|
|
|
|
*/
|
|
|
|
|
data->imap = ~0UL;
|
|
|
|
|
data->iclr = ~0UL;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
out:
|
|
|
|
|
return bucket->virt_irq;
|
|
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
|
[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 01:41:02 +00:00
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
|
|
|
unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p,
|
|
|
|
|
unsigned int msi_start, unsigned int msi_end)
|
|
|
|
|
{
|
|
|
|
|
struct ino_bucket *bucket;
|
|
|
|
|
struct irq_handler_data *data;
|
|
|
|
|
unsigned long sysino;
|
|
|
|
|
unsigned int devino;
|
|
|
|
|
|
|
|
|
|
BUG_ON(tlb_type != hypervisor);
|
|
|
|
|
|
|
|
|
|
/* Find a free devino in the given range. */
|
|
|
|
|
for (devino = msi_start; devino < msi_end; devino++) {
|
|
|
|
|
sysino = sun4v_devino_to_sysino(devhandle, devino);
|
|
|
|
|
bucket = &ivector_table[sysino];
|
|
|
|
|
if (!bucket->virt_irq)
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
if (devino >= msi_end)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
sysino = sun4v_devino_to_sysino(devhandle, devino);
|
|
|
|
|
bucket = &ivector_table[sysino];
|
|
|
|
|
bucket->virt_irq = virt_irq_alloc(__irq(bucket));
|
|
|
|
|
*virt_irq_p = bucket->virt_irq;
|
|
|
|
|
set_irq_chip(bucket->virt_irq, &sun4v_msi);
|
|
|
|
|
|
|
|
|
|
data = get_irq_chip_data(bucket->virt_irq);
|
|
|
|
|
if (unlikely(data))
|
|
|
|
|
return devino;
|
|
|
|
|
|
|
|
|
|
data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
|
|
|
|
|
if (unlikely(!data)) {
|
|
|
|
|
prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
|
|
|
|
|
prom_halt();
|
|
|
|
|
}
|
|
|
|
|
set_irq_chip_data(bucket->virt_irq, data);
|
|
|
|
|
|
|
|
|
|
data->imap = ~0UL;
|
|
|
|
|
data->iclr = ~0UL;
|
|
|
|
|
|
|
|
|
|
return devino;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void sun4v_destroy_msi(unsigned int virt_irq)
|
|
|
|
|
{
|
|
|
|
|
virt_irq_free(virt_irq);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
void ack_bad_irq(unsigned int virt_irq)
|
|
|
|
|
{
|
|
|
|
|
struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
|
|
|
|
|
unsigned int ino = 0xdeadbeef;
|
2006-02-15 09:18:19 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
if (bucket)
|
|
|
|
|
ino = bucket - &ivector_table[0];
|
2006-06-20 08:20:30 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
|
|
|
|
|
ino, virt_irq);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
2006-06-20 08:20:00 +00:00
|
|
|
#ifndef CONFIG_SMP
|
2006-10-09 10:51:14 +00:00
|
|
|
extern irqreturn_t timer_interrupt(int, void *);
|
2006-06-20 08:20:00 +00:00
|
|
|
|
|
|
|
|
void timer_irq(int irq, struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
unsigned long clr_mask = 1 << irq;
|
|
|
|
|
unsigned long tick_mask = tick_ops->softint_mask;
|
2006-10-09 10:51:14 +00:00
|
|
|
struct pt_regs *old_regs;
|
2006-06-20 08:20:00 +00:00
|
|
|
|
|
|
|
|
if (get_softint() & tick_mask) {
|
|
|
|
|
irq = 0;
|
|
|
|
|
clr_mask = tick_mask;
|
|
|
|
|
}
|
|
|
|
|
clear_softint(clr_mask);
|
|
|
|
|
|
2006-10-09 10:51:14 +00:00
|
|
|
old_regs = set_irq_regs(regs);
|
2006-06-20 08:20:00 +00:00
|
|
|
irq_enter();
|
2006-06-20 08:23:32 +00:00
|
|
|
|
2006-06-20 08:22:35 +00:00
|
|
|
kstat_this_cpu.irqs[0]++;
|
2006-10-09 10:51:14 +00:00
|
|
|
timer_interrupt(irq, NULL);
|
2006-06-20 08:23:32 +00:00
|
|
|
|
2006-06-20 08:20:00 +00:00
|
|
|
irq_exit();
|
2006-10-09 10:51:14 +00:00
|
|
|
set_irq_regs(old_regs);
|
2006-06-20 08:20:00 +00:00
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
void handler_irq(int irq, struct pt_regs *regs)
|
|
|
|
|
{
|
2006-06-20 08:23:32 +00:00
|
|
|
struct ino_bucket *bucket;
|
2006-10-08 12:23:28 +00:00
|
|
|
struct pt_regs *old_regs;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
|
clear_softint(1 << irq);
|
|
|
|
|
|
2006-10-08 12:23:28 +00:00
|
|
|
old_regs = set_irq_regs(regs);
|
2005-04-16 22:20:36 +00:00
|
|
|
irq_enter();
|
|
|
|
|
|
|
|
|
|
/* Sliiiick... */
|
2006-06-20 08:23:32 +00:00
|
|
|
bucket = __bucket(xchg32(irq_work(smp_processor_id()), 0));
|
|
|
|
|
while (bucket) {
|
|
|
|
|
struct ino_bucket *next = __bucket(bucket->irq_chain);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
bucket->irq_chain = 0;
|
2006-10-08 12:23:28 +00:00
|
|
|
__do_IRQ(bucket->virt_irq);
|
2006-06-20 08:20:00 +00:00
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
bucket = next;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2006-06-20 08:23:32 +00:00
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
irq_exit();
|
2006-10-08 12:23:28 +00:00
|
|
|
set_irq_regs(old_regs);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
2005-07-25 02:36:13 +00:00
|
|
|
struct sun5_timer {
|
|
|
|
|
u64 count0;
|
|
|
|
|
u64 limit0;
|
|
|
|
|
u64 count1;
|
|
|
|
|
u64 limit1;
|
|
|
|
|
};
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2005-07-25 02:36:13 +00:00
|
|
|
static struct sun5_timer *prom_timers;
|
2005-04-16 22:20:36 +00:00
|
|
|
static u64 prom_limit0, prom_limit1;
|
|
|
|
|
|
|
|
|
|
static void map_prom_timers(void)
|
|
|
|
|
{
|
2006-06-23 03:21:22 +00:00
|
|
|
struct device_node *dp;
|
|
|
|
|
unsigned int *addr;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
|
/* PROM timer node hangs out in the top level of device siblings... */
|
2006-06-23 03:21:22 +00:00
|
|
|
dp = of_find_node_by_path("/");
|
|
|
|
|
dp = dp->child;
|
|
|
|
|
while (dp) {
|
|
|
|
|
if (!strcmp(dp->name, "counter-timer"))
|
|
|
|
|
break;
|
|
|
|
|
dp = dp->sibling;
|
|
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
|
/* Assume if node is not present, PROM uses different tick mechanism
|
|
|
|
|
* which we should not care about.
|
|
|
|
|
*/
|
2006-06-23 03:21:22 +00:00
|
|
|
if (!dp) {
|
2005-04-16 22:20:36 +00:00
|
|
|
prom_timers = (struct sun5_timer *) 0;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* If PROM is really using this, it must be mapped by him. */
|
2006-06-23 03:21:22 +00:00
|
|
|
addr = of_get_property(dp, "address", NULL);
|
|
|
|
|
if (!addr) {
|
2005-04-16 22:20:36 +00:00
|
|
|
prom_printf("PROM does not have timer mapped, trying to continue.\n");
|
|
|
|
|
prom_timers = (struct sun5_timer *) 0;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void kill_prom_timer(void)
|
|
|
|
|
{
|
|
|
|
|
if (!prom_timers)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/* Save them away for later. */
|
|
|
|
|
prom_limit0 = prom_timers->limit0;
|
|
|
|
|
prom_limit1 = prom_timers->limit1;
|
|
|
|
|
|
|
|
|
|
/* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
|
|
|
|
|
* We turn both off here just to be paranoid.
|
|
|
|
|
*/
|
|
|
|
|
prom_timers->limit0 = 0;
|
|
|
|
|
prom_timers->limit1 = 0;
|
|
|
|
|
|
|
|
|
|
/* Wheee, eat the interrupt packet too... */
|
|
|
|
|
__asm__ __volatile__(
|
|
|
|
|
" mov 0x40, %%g2\n"
|
|
|
|
|
" ldxa [%%g0] %0, %%g1\n"
|
|
|
|
|
" ldxa [%%g2] %1, %%g1\n"
|
|
|
|
|
" stxa %%g0, [%%g0] %0\n"
|
|
|
|
|
" membar #Sync\n"
|
|
|
|
|
: /* no outputs */
|
|
|
|
|
: "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
|
|
|
|
|
: "g1", "g2");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void init_irqwork_curcpu(void)
|
|
|
|
|
{
|
|
|
|
|
int cpu = hard_smp_processor_id();
|
|
|
|
|
|
2006-06-20 08:20:00 +00:00
|
|
|
trap_block[cpu].irq_worklist = 0;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
2006-02-12 07:07:13 +00:00
|
|
|
static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
|
2006-02-08 08:08:23 +00:00
|
|
|
{
|
2006-02-16 22:26:53 +00:00
|
|
|
unsigned long num_entries = 128;
|
|
|
|
|
unsigned long status;
|
|
|
|
|
|
|
|
|
|
status = sun4v_cpu_qconf(type, paddr, num_entries);
|
|
|
|
|
if (status != HV_EOK) {
|
|
|
|
|
prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
|
|
|
|
|
"err %lu\n", type, paddr, num_entries, status);
|
2006-02-08 08:08:23 +00:00
|
|
|
prom_halt();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2006-02-12 07:07:13 +00:00
|
|
|
static void __cpuinit sun4v_register_mondo_queues(int this_cpu)
|
2006-02-08 10:53:50 +00:00
|
|
|
{
|
2006-02-12 07:07:13 +00:00
|
|
|
struct trap_per_cpu *tb = &trap_block[this_cpu];
|
|
|
|
|
|
|
|
|
|
register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
|
|
|
|
|
register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
|
|
|
|
|
register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
|
|
|
|
|
register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem)
|
|
|
|
|
{
|
|
|
|
|
void *page;
|
|
|
|
|
|
|
|
|
|
if (use_bootmem)
|
|
|
|
|
page = alloc_bootmem_low_pages(PAGE_SIZE);
|
|
|
|
|
else
|
|
|
|
|
page = (void *) get_zeroed_page(GFP_ATOMIC);
|
|
|
|
|
|
|
|
|
|
if (!page) {
|
|
|
|
|
prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
|
|
|
|
|
prom_halt();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
*pa_ptr = __pa(page);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem)
|
|
|
|
|
{
|
|
|
|
|
void *page;
|
|
|
|
|
|
|
|
|
|
if (use_bootmem)
|
|
|
|
|
page = alloc_bootmem_low_pages(PAGE_SIZE);
|
|
|
|
|
else
|
|
|
|
|
page = (void *) get_zeroed_page(GFP_ATOMIC);
|
2006-02-08 10:53:50 +00:00
|
|
|
|
|
|
|
|
if (!page) {
|
|
|
|
|
prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
|
|
|
|
|
prom_halt();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
*pa_ptr = __pa(page);
|
|
|
|
|
}
|
|
|
|
|
|
2006-02-12 07:07:13 +00:00
|
|
|
static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem)
|
2006-02-09 00:41:20 +00:00
|
|
|
{
|
|
|
|
|
#ifdef CONFIG_SMP
|
2006-02-12 07:07:13 +00:00
|
|
|
void *page;
|
2006-02-09 00:41:20 +00:00
|
|
|
|
|
|
|
|
BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
|
|
|
|
|
|
2006-02-12 07:07:13 +00:00
|
|
|
if (use_bootmem)
|
|
|
|
|
page = alloc_bootmem_low_pages(PAGE_SIZE);
|
|
|
|
|
else
|
|
|
|
|
page = (void *) get_zeroed_page(GFP_ATOMIC);
|
|
|
|
|
|
2006-02-09 00:41:20 +00:00
|
|
|
if (!page) {
|
|
|
|
|
prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
|
|
|
|
|
prom_halt();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
tb->cpu_mondo_block_pa = __pa(page);
|
|
|
|
|
tb->cpu_list_pa = __pa(page + 64);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
2006-02-12 07:07:13 +00:00
|
|
|
/* Allocate and register the mondo and error queues for this cpu. */
|
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 09:29:17 +00:00
|
|
|
void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load)
|
2006-02-08 08:08:23 +00:00
|
|
|
{
|
|
|
|
|
struct trap_per_cpu *tb = &trap_block[cpu];
|
|
|
|
|
|
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 09:29:17 +00:00
|
|
|
if (alloc) {
|
|
|
|
|
alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem);
|
|
|
|
|
alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem);
|
|
|
|
|
alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem);
|
|
|
|
|
alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem);
|
|
|
|
|
alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem);
|
|
|
|
|
alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem);
|
2006-02-09 00:41:20 +00:00
|
|
|
|
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 09:29:17 +00:00
|
|
|
init_cpu_send_mondo_info(tb, use_bootmem);
|
|
|
|
|
}
|
2006-02-09 00:41:20 +00:00
|
|
|
|
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 09:29:17 +00:00
|
|
|
if (load) {
|
|
|
|
|
if (cpu != hard_smp_processor_id()) {
|
|
|
|
|
prom_printf("SUN4V: init mondo on cpu %d not %d\n",
|
|
|
|
|
cpu, hard_smp_processor_id());
|
|
|
|
|
prom_halt();
|
|
|
|
|
}
|
|
|
|
|
sun4v_register_mondo_queues(cpu);
|
|
|
|
|
}
|
2006-02-08 08:08:23 +00:00
|
|
|
}
|
|
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
static struct irqaction timer_irq_action = {
|
|
|
|
|
.name = "timer",
|
|
|
|
|
};
|
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/* Only invoked on boot processor. */
|
|
|
|
|
void __init init_IRQ(void)
|
|
|
|
|
{
|
|
|
|
|
map_prom_timers();
|
|
|
|
|
kill_prom_timer();
|
|
|
|
|
memset(&ivector_table[0], 0, sizeof(ivector_table));
|
|
|
|
|
|
2006-02-08 08:08:23 +00:00
|
|
|
if (tlb_type == hypervisor)
|
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 09:29:17 +00:00
|
|
|
sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
|
2006-02-08 08:08:23 +00:00
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/* We need to clear any IRQ's pending in the soft interrupt
|
|
|
|
|
* registers, a spurious one could be left around from the
|
|
|
|
|
* PROM timer which we just disabled.
|
|
|
|
|
*/
|
|
|
|
|
clear_softint(get_softint());
|
|
|
|
|
|
|
|
|
|
/* Now that ivector table is initialized, it is safe
|
|
|
|
|
* to receive IRQ vector traps. We will normally take
|
|
|
|
|
* one or two right now, in case some device PROM used
|
|
|
|
|
* to boot us wants to speak to us. We just ignore them.
|
|
|
|
|
*/
|
|
|
|
|
__asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
|
|
|
|
|
"or %%g1, %0, %%g1\n\t"
|
|
|
|
|
"wrpr %%g1, 0x0, %%pstate"
|
|
|
|
|
: /* No outputs */
|
|
|
|
|
: "i" (PSTATE_IE)
|
|
|
|
|
: "g1");
|
|
|
|
|
|
2006-06-20 08:23:32 +00:00
|
|
|
irq_desc[0].action = &timer_irq_action;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|