2009-12-11 09:24:15 +00:00
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/*
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* Copyright (C) 2006 Ben Skeggs.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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/*
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* Authors:
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* Ben Skeggs <darktama@iinet.net.au>
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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2010-09-01 05:24:28 +00:00
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#include "nouveau_ramht.h"
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2010-11-15 01:54:21 +00:00
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#include "nouveau_vm.h"
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2011-02-07 03:29:23 +00:00
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#include "nv50_display.h"
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2009-12-11 09:24:15 +00:00
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2010-10-20 00:39:35 +00:00
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struct nouveau_gpuobj_method {
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struct list_head head;
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u32 mthd;
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int (*exec)(struct nouveau_channel *, u32 class, u32 mthd, u32 data);
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};
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struct nouveau_gpuobj_class {
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struct list_head head;
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struct list_head methods;
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u32 id;
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u32 engine;
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};
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int
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nouveau_gpuobj_class_new(struct drm_device *dev, u32 class, u32 engine)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj_class *oc;
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oc = kzalloc(sizeof(*oc), GFP_KERNEL);
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if (!oc)
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return -ENOMEM;
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INIT_LIST_HEAD(&oc->methods);
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oc->id = class;
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oc->engine = engine;
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list_add(&oc->head, &dev_priv->classes);
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return 0;
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}
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int
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nouveau_gpuobj_mthd_new(struct drm_device *dev, u32 class, u32 mthd,
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int (*exec)(struct nouveau_channel *, u32, u32, u32))
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj_method *om;
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struct nouveau_gpuobj_class *oc;
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list_for_each_entry(oc, &dev_priv->classes, head) {
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if (oc->id == class)
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goto found;
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}
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return -EINVAL;
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found:
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om = kzalloc(sizeof(*om), GFP_KERNEL);
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if (!om)
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return -ENOMEM;
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om->mthd = mthd;
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om->exec = exec;
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list_add(&om->head, &oc->methods);
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return 0;
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}
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int
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nouveau_gpuobj_mthd_call(struct nouveau_channel *chan,
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u32 class, u32 mthd, u32 data)
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{
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struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
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struct nouveau_gpuobj_method *om;
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struct nouveau_gpuobj_class *oc;
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list_for_each_entry(oc, &dev_priv->classes, head) {
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if (oc->id != class)
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continue;
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list_for_each_entry(om, &oc->methods, head) {
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if (om->mthd == mthd)
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return om->exec(chan, class, mthd, data);
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}
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}
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return -ENOENT;
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}
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2010-11-03 03:16:18 +00:00
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int
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nouveau_gpuobj_mthd_call2(struct drm_device *dev, int chid,
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u32 class, u32 mthd, u32 data)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_channel *chan = NULL;
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unsigned long flags;
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int ret = -EINVAL;
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spin_lock_irqsave(&dev_priv->channels.lock, flags);
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2011-06-23 05:47:32 +00:00
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if (chid >= 0 && chid < dev_priv->engine.fifo.channels)
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2010-11-03 03:16:18 +00:00
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chan = dev_priv->channels.ptr[chid];
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if (chan)
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ret = nouveau_gpuobj_mthd_call(chan, class, mthd, data);
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spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
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return ret;
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}
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2009-12-11 09:24:15 +00:00
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/* NVidia uses context objects to drive drawing operations.
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Context objects can be selected into 8 subchannels in the FIFO,
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and then used via DMA command buffers.
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A context object is referenced by a user defined handle (CARD32). The HW
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looks up graphics objects in a hash table in the instance RAM.
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An entry in the hash table consists of 2 CARD32. The first CARD32 contains
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the handle, the second one a bitfield, that contains the address of the
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object in instance RAM.
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The format of the second CARD32 seems to be:
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NV4 to NV30:
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15: 0 instance_addr >> 4
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17:16 engine (here uses 1 = graphics)
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28:24 channel id (here uses 0)
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31 valid (use 1)
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NV40:
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15: 0 instance_addr >> 4 (maybe 19-0)
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21:20 engine (here uses 1 = graphics)
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I'm unsure about the other bits, but using 0 seems to work.
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The key into the hash table depends on the object handle and channel id and
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is given as:
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*/
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int
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nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
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uint32_t size, int align, uint32_t flags,
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struct nouveau_gpuobj **gpuobj_ret)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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2010-11-01 01:45:02 +00:00
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struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
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2009-12-11 09:24:15 +00:00
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struct nouveau_gpuobj *gpuobj;
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2010-09-01 05:24:33 +00:00
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struct drm_mm_node *ramin = NULL;
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2010-11-01 01:45:02 +00:00
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int ret, i;
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2009-12-11 09:24:15 +00:00
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NV_DEBUG(dev, "ch%d size=%u align=%d flags=0x%08x\n",
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chan ? chan->id : -1, size, align, flags);
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gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
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if (!gpuobj)
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return -ENOMEM;
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NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
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2010-09-01 05:24:29 +00:00
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gpuobj->dev = dev;
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2009-12-11 09:24:15 +00:00
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gpuobj->flags = flags;
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2010-09-01 05:24:37 +00:00
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kref_init(&gpuobj->refcount);
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2010-09-01 05:24:32 +00:00
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gpuobj->size = size;
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2009-12-11 09:24:15 +00:00
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2010-09-01 05:24:38 +00:00
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spin_lock(&dev_priv->ramin_lock);
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2009-12-11 09:24:15 +00:00
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list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
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2010-09-01 05:24:38 +00:00
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spin_unlock(&dev_priv->ramin_lock);
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2009-12-11 09:24:15 +00:00
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2011-06-03 04:23:30 +00:00
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if (!(flags & NVOBJ_FLAG_VM) && chan) {
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2010-09-01 05:24:33 +00:00
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ramin = drm_mm_search_free(&chan->ramin_heap, size, align, 0);
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if (ramin)
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ramin = drm_mm_get_block(ramin, size, align);
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if (!ramin) {
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nouveau_gpuobj_ref(NULL, &gpuobj);
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return -ENOMEM;
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}
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2009-12-11 09:24:15 +00:00
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2010-11-01 01:45:02 +00:00
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gpuobj->pinst = chan->ramin->pinst;
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if (gpuobj->pinst != ~0)
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gpuobj->pinst += ramin->start;
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2010-06-01 05:32:24 +00:00
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2010-11-20 13:42:57 +00:00
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gpuobj->cinst = ramin->start;
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2010-11-01 01:45:02 +00:00
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gpuobj->vinst = ramin->start + chan->ramin->vinst;
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gpuobj->node = ramin;
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} else {
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2011-06-03 04:23:30 +00:00
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ret = instmem->get(gpuobj, chan, size, align);
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2009-12-11 09:24:15 +00:00
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if (ret) {
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2010-09-01 05:24:31 +00:00
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nouveau_gpuobj_ref(NULL, &gpuobj);
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2009-12-11 09:24:15 +00:00
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return ret;
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}
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2010-09-01 05:24:33 +00:00
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2010-11-01 01:45:02 +00:00
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ret = -ENOSYS;
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2010-08-27 00:00:25 +00:00
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if (!(flags & NVOBJ_FLAG_DONT_MAP))
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2010-11-01 01:45:02 +00:00
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ret = instmem->map(gpuobj);
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if (ret)
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2010-09-01 05:24:33 +00:00
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gpuobj->pinst = ~0;
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2010-11-01 01:45:02 +00:00
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gpuobj->cinst = NVOBJ_CINST_GLOBAL;
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2010-09-01 05:24:30 +00:00
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}
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2009-12-11 09:24:15 +00:00
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if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
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2010-09-01 05:24:32 +00:00
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for (i = 0; i < gpuobj->size; i += 4)
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2010-09-01 05:24:29 +00:00
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nv_wo32(gpuobj, i, 0);
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2010-11-01 01:45:02 +00:00
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instmem->flush(dev);
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2009-12-11 09:24:15 +00:00
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}
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2010-09-01 05:24:31 +00:00
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2009-12-11 09:24:15 +00:00
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*gpuobj_ret = gpuobj;
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return 0;
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}
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int
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2010-09-01 05:24:34 +00:00
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nouveau_gpuobj_init(struct drm_device *dev)
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2009-12-11 09:24:15 +00:00
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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NV_DEBUG(dev, "\n");
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INIT_LIST_HEAD(&dev_priv->gpuobj_list);
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2010-10-19 10:06:01 +00:00
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INIT_LIST_HEAD(&dev_priv->classes);
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2010-09-01 05:24:33 +00:00
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spin_lock_init(&dev_priv->ramin_lock);
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dev_priv->ramin_base = ~0;
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2009-12-11 09:24:15 +00:00
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return 0;
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}
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void
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nouveau_gpuobj_takedown(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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2010-10-20 00:39:35 +00:00
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struct nouveau_gpuobj_method *om, *tm;
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struct nouveau_gpuobj_class *oc, *tc;
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2009-12-11 09:24:15 +00:00
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NV_DEBUG(dev, "\n");
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2010-10-20 00:39:35 +00:00
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list_for_each_entry_safe(oc, tc, &dev_priv->classes, head) {
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list_for_each_entry_safe(om, tm, &oc->methods, head) {
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list_del(&om->head);
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kfree(om);
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}
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list_del(&oc->head);
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kfree(oc);
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}
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2010-09-01 05:24:37 +00:00
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BUG_ON(!list_empty(&dev_priv->gpuobj_list));
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2009-12-11 09:24:15 +00:00
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}
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2010-09-01 05:24:39 +00:00
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2010-09-01 05:24:37 +00:00
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static void
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nouveau_gpuobj_del(struct kref *ref)
|
2009-12-11 09:24:15 +00:00
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{
|
2010-09-01 05:24:37 +00:00
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struct nouveau_gpuobj *gpuobj =
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container_of(ref, struct nouveau_gpuobj, refcount);
|
2010-09-01 05:24:31 +00:00
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struct drm_device *dev = gpuobj->dev;
|
2009-12-11 09:24:15 +00:00
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struct drm_nouveau_private *dev_priv = dev->dev_private;
|
2010-11-01 01:45:02 +00:00
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struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
|
2009-12-11 09:24:15 +00:00
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int i;
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|
2010-09-01 05:24:31 +00:00
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NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
|
2009-12-11 09:24:15 +00:00
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|
2010-11-01 01:45:02 +00:00
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if (gpuobj->node && (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE)) {
|
2010-09-01 05:24:32 +00:00
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for (i = 0; i < gpuobj->size; i += 4)
|
2010-09-01 05:24:29 +00:00
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nv_wo32(gpuobj, i, 0);
|
2010-11-01 01:45:02 +00:00
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|
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instmem->flush(dev);
|
2009-12-11 09:24:15 +00:00
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}
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|
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|
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if (gpuobj->dtor)
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|
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gpuobj->dtor(dev, gpuobj);
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|
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|
2010-11-01 01:45:02 +00:00
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|
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if (gpuobj->cinst == NVOBJ_CINST_GLOBAL) {
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|
|
if (gpuobj->node) {
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|
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instmem->unmap(gpuobj);
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|
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instmem->put(gpuobj);
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|
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}
|
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|
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} else {
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|
|
|
if (gpuobj->node) {
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|
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spin_lock(&dev_priv->ramin_lock);
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|
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drm_mm_put_block(gpuobj->node);
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|
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spin_unlock(&dev_priv->ramin_lock);
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|
|
|
}
|
|
|
|
}
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-09-01 05:24:38 +00:00
|
|
|
spin_lock(&dev_priv->ramin_lock);
|
2009-12-11 09:24:15 +00:00
|
|
|
list_del(&gpuobj->list);
|
2010-09-01 05:24:38 +00:00
|
|
|
spin_unlock(&dev_priv->ramin_lock);
|
2009-12-11 09:24:15 +00:00
|
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|
|
kfree(gpuobj);
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|
|
}
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|
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|
2010-09-01 05:24:31 +00:00
|
|
|
void
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|
|
|
nouveau_gpuobj_ref(struct nouveau_gpuobj *ref, struct nouveau_gpuobj **ptr)
|
2009-12-11 09:24:15 +00:00
|
|
|
{
|
2010-09-01 05:24:31 +00:00
|
|
|
if (ref)
|
2010-09-01 05:24:37 +00:00
|
|
|
kref_get(&ref->refcount);
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-09-01 05:24:37 +00:00
|
|
|
if (*ptr)
|
|
|
|
kref_put(&(*ptr)->refcount, nouveau_gpuobj_del);
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-09-01 05:24:31 +00:00
|
|
|
*ptr = ref;
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
2010-09-01 05:24:32 +00:00
|
|
|
nouveau_gpuobj_new_fake(struct drm_device *dev, u32 pinst, u64 vinst,
|
|
|
|
u32 size, u32 flags, struct nouveau_gpuobj **pgpuobj)
|
2009-12-11 09:24:15 +00:00
|
|
|
{
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
struct nouveau_gpuobj *gpuobj = NULL;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
NV_DEBUG(dev,
|
2010-09-01 05:24:32 +00:00
|
|
|
"pinst=0x%08x vinst=0x%010llx size=0x%08x flags=0x%08x\n",
|
|
|
|
pinst, vinst, size, flags);
|
2009-12-11 09:24:15 +00:00
|
|
|
|
|
|
|
gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
|
|
|
|
if (!gpuobj)
|
|
|
|
return -ENOMEM;
|
|
|
|
NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
|
2010-09-01 05:24:29 +00:00
|
|
|
gpuobj->dev = dev;
|
2010-09-01 05:24:32 +00:00
|
|
|
gpuobj->flags = flags;
|
2010-09-01 05:24:37 +00:00
|
|
|
kref_init(&gpuobj->refcount);
|
2010-09-01 05:24:32 +00:00
|
|
|
gpuobj->size = size;
|
|
|
|
gpuobj->pinst = pinst;
|
2010-11-01 01:45:02 +00:00
|
|
|
gpuobj->cinst = NVOBJ_CINST_GLOBAL;
|
2010-09-01 05:24:32 +00:00
|
|
|
gpuobj->vinst = vinst;
|
2010-09-01 05:24:30 +00:00
|
|
|
|
2009-12-11 09:24:15 +00:00
|
|
|
if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
|
2010-09-01 05:24:32 +00:00
|
|
|
for (i = 0; i < gpuobj->size; i += 4)
|
2010-09-01 05:24:29 +00:00
|
|
|
nv_wo32(gpuobj, i, 0);
|
2010-07-08 01:29:10 +00:00
|
|
|
dev_priv->engine.instmem.flush(dev);
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
2010-09-01 05:24:38 +00:00
|
|
|
spin_lock(&dev_priv->ramin_lock);
|
2010-09-01 05:24:32 +00:00
|
|
|
list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
|
2010-09-01 05:24:38 +00:00
|
|
|
spin_unlock(&dev_priv->ramin_lock);
|
2010-09-01 05:24:32 +00:00
|
|
|
*pgpuobj = gpuobj;
|
2009-12-11 09:24:15 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
DMA objects are used to reference a piece of memory in the
|
|
|
|
framebuffer, PCI or AGP address space. Each object is 16 bytes big
|
|
|
|
and looks as follows:
|
|
|
|
|
|
|
|
entry[0]
|
|
|
|
11:0 class (seems like I can always use 0 here)
|
|
|
|
12 page table present?
|
|
|
|
13 page entry linear?
|
|
|
|
15:14 access: 0 rw, 1 ro, 2 wo
|
|
|
|
17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP
|
|
|
|
31:20 dma adjust (bits 0-11 of the address)
|
|
|
|
entry[1]
|
|
|
|
dma limit (size of transfer)
|
|
|
|
entry[X]
|
|
|
|
1 0 readonly, 1 readwrite
|
|
|
|
31:12 dma frame address of the page (bits 12-31 of the address)
|
|
|
|
entry[N]
|
|
|
|
page table terminator, same value as the first pte, as does nvidia
|
|
|
|
rivatv uses 0xffffffff
|
|
|
|
|
|
|
|
Non linear page tables need a list of frame addresses afterwards,
|
|
|
|
the rivatv project has some info on this.
|
|
|
|
|
|
|
|
The method below creates a DMA object in instance RAM and returns a handle
|
|
|
|
to it that can be used to set up context objects.
|
|
|
|
*/
|
2010-11-16 01:50:09 +00:00
|
|
|
|
|
|
|
void
|
|
|
|
nv50_gpuobj_dma_init(struct nouveau_gpuobj *obj, u32 offset, int class,
|
|
|
|
u64 base, u64 size, int target, int access,
|
|
|
|
u32 type, u32 comp)
|
2009-12-11 09:24:15 +00:00
|
|
|
{
|
2010-11-16 01:50:09 +00:00
|
|
|
struct drm_nouveau_private *dev_priv = obj->dev->dev_private;
|
|
|
|
struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
|
|
|
|
u32 flags0;
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-11-16 01:50:09 +00:00
|
|
|
flags0 = (comp << 29) | (type << 22) | class;
|
|
|
|
flags0 |= 0x00100000;
|
|
|
|
|
|
|
|
switch (access) {
|
|
|
|
case NV_MEM_ACCESS_RO: flags0 |= 0x00040000; break;
|
|
|
|
case NV_MEM_ACCESS_RW:
|
|
|
|
case NV_MEM_ACCESS_WO: flags0 |= 0x00080000; break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2009-12-11 09:24:15 +00:00
|
|
|
|
|
|
|
switch (target) {
|
2010-11-16 01:50:09 +00:00
|
|
|
case NV_MEM_TARGET_VRAM:
|
|
|
|
flags0 |= 0x00010000;
|
|
|
|
break;
|
|
|
|
case NV_MEM_TARGET_PCI:
|
|
|
|
flags0 |= 0x00020000;
|
|
|
|
break;
|
|
|
|
case NV_MEM_TARGET_PCI_NOSNOOP:
|
|
|
|
flags0 |= 0x00030000;
|
2009-12-11 09:24:15 +00:00
|
|
|
break;
|
2010-11-16 01:50:09 +00:00
|
|
|
case NV_MEM_TARGET_GART:
|
2010-11-16 00:13:05 +00:00
|
|
|
base += dev_priv->gart_info.aper_base;
|
2009-12-11 09:24:15 +00:00
|
|
|
default:
|
2010-11-16 01:50:09 +00:00
|
|
|
flags0 &= ~0x00100000;
|
2009-12-11 09:24:15 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2010-11-16 01:50:09 +00:00
|
|
|
/* convert to base + limit */
|
|
|
|
size = (base + size) - 1;
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-11-16 01:50:09 +00:00
|
|
|
nv_wo32(obj, offset + 0x00, flags0);
|
|
|
|
nv_wo32(obj, offset + 0x04, lower_32_bits(size));
|
|
|
|
nv_wo32(obj, offset + 0x08, lower_32_bits(base));
|
|
|
|
nv_wo32(obj, offset + 0x0c, upper_32_bits(size) << 24 |
|
|
|
|
upper_32_bits(base));
|
|
|
|
nv_wo32(obj, offset + 0x10, 0x00000000);
|
|
|
|
nv_wo32(obj, offset + 0x14, 0x00000000);
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-11-16 01:50:09 +00:00
|
|
|
pinstmem->flush(obj->dev);
|
|
|
|
}
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-11-16 01:50:09 +00:00
|
|
|
int
|
|
|
|
nv50_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base, u64 size,
|
|
|
|
int target, int access, u32 type, u32 comp,
|
|
|
|
struct nouveau_gpuobj **pobj)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = chan->dev;
|
|
|
|
int ret;
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-11-26 00:32:22 +00:00
|
|
|
ret = nouveau_gpuobj_new(dev, chan, 24, 16, NVOBJ_FLAG_ZERO_FREE, pobj);
|
2010-11-16 01:50:09 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-11-16 01:50:09 +00:00
|
|
|
nv50_gpuobj_dma_init(*pobj, 0, class, base, size, target,
|
|
|
|
access, type, comp);
|
2009-12-11 09:24:15 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
2010-11-16 01:50:09 +00:00
|
|
|
nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base,
|
|
|
|
u64 size, int access, int target,
|
|
|
|
struct nouveau_gpuobj **pobj)
|
2009-12-11 09:24:15 +00:00
|
|
|
{
|
2010-11-16 01:50:09 +00:00
|
|
|
struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
|
2009-12-11 09:24:15 +00:00
|
|
|
struct drm_device *dev = chan->dev;
|
2010-11-16 01:50:09 +00:00
|
|
|
struct nouveau_gpuobj *obj;
|
2010-12-08 01:37:12 +00:00
|
|
|
u32 flags0, flags2;
|
2009-12-11 09:24:15 +00:00
|
|
|
int ret;
|
|
|
|
|
2010-11-16 01:50:09 +00:00
|
|
|
if (dev_priv->card_type >= NV_50) {
|
|
|
|
u32 comp = (target == NV_MEM_TARGET_VM) ? NV_MEM_COMP_VM : 0;
|
|
|
|
u32 type = (target == NV_MEM_TARGET_VM) ? NV_MEM_TYPE_VM : 0;
|
|
|
|
|
|
|
|
return nv50_gpuobj_dma_new(chan, class, base, size,
|
|
|
|
target, access, type, comp, pobj);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (target == NV_MEM_TARGET_GART) {
|
2011-01-11 04:10:09 +00:00
|
|
|
struct nouveau_gpuobj *gart = dev_priv->gart_info.sg_ctxdma;
|
|
|
|
|
|
|
|
if (dev_priv->gart_info.type == NOUVEAU_GART_PDMA) {
|
|
|
|
if (base == 0) {
|
|
|
|
nouveau_gpuobj_ref(gart, pobj);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
base = nouveau_sgdma_get_physical(dev, base);
|
2010-11-16 01:50:09 +00:00
|
|
|
target = NV_MEM_TARGET_PCI;
|
|
|
|
} else {
|
2011-01-11 04:10:09 +00:00
|
|
|
base += dev_priv->gart_info.aper_base;
|
|
|
|
if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
|
|
|
|
target = NV_MEM_TARGET_PCI_NOSNOOP;
|
|
|
|
else
|
|
|
|
target = NV_MEM_TARGET_PCI;
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-11-16 01:50:09 +00:00
|
|
|
flags0 = class;
|
|
|
|
flags0 |= 0x00003000; /* PT present, PT linear */
|
|
|
|
flags2 = 0;
|
|
|
|
|
|
|
|
switch (target) {
|
|
|
|
case NV_MEM_TARGET_PCI:
|
|
|
|
flags0 |= 0x00020000;
|
|
|
|
break;
|
|
|
|
case NV_MEM_TARGET_PCI_NOSNOOP:
|
|
|
|
flags0 |= 0x00030000;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (access) {
|
|
|
|
case NV_MEM_ACCESS_RO:
|
|
|
|
flags0 |= 0x00004000;
|
|
|
|
break;
|
|
|
|
case NV_MEM_ACCESS_WO:
|
|
|
|
flags0 |= 0x00008000;
|
|
|
|
default:
|
|
|
|
flags2 |= 0x00000002;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
flags0 |= (base & 0x00000fff) << 20;
|
|
|
|
flags2 |= (base & 0xfffff000);
|
|
|
|
|
2010-11-26 00:32:22 +00:00
|
|
|
ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
|
2010-11-16 01:50:09 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
nv_wo32(obj, 0x00, flags0);
|
|
|
|
nv_wo32(obj, 0x04, size - 1);
|
|
|
|
nv_wo32(obj, 0x08, flags2);
|
|
|
|
nv_wo32(obj, 0x0c, flags2);
|
|
|
|
|
|
|
|
obj->engine = NVOBJ_ENGINE_SW;
|
|
|
|
obj->class = class;
|
|
|
|
*pobj = obj;
|
|
|
|
return 0;
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Context objects in the instance RAM have the following structure.
|
|
|
|
* On NV40 they are 32 byte long, on NV30 and smaller 16 bytes.
|
|
|
|
|
|
|
|
NV4 - NV30:
|
|
|
|
|
|
|
|
entry[0]
|
|
|
|
11:0 class
|
|
|
|
12 chroma key enable
|
|
|
|
13 user clip enable
|
|
|
|
14 swizzle enable
|
|
|
|
17:15 patch config:
|
|
|
|
scrcopy_and, rop_and, blend_and, scrcopy, srccopy_pre, blend_pre
|
|
|
|
18 synchronize enable
|
|
|
|
19 endian: 1 big, 0 little
|
|
|
|
21:20 dither mode
|
|
|
|
23 single step enable
|
|
|
|
24 patch status: 0 invalid, 1 valid
|
|
|
|
25 context_surface 0: 1 valid
|
|
|
|
26 context surface 1: 1 valid
|
|
|
|
27 context pattern: 1 valid
|
|
|
|
28 context rop: 1 valid
|
|
|
|
29,30 context beta, beta4
|
|
|
|
entry[1]
|
|
|
|
7:0 mono format
|
|
|
|
15:8 color format
|
|
|
|
31:16 notify instance address
|
|
|
|
entry[2]
|
|
|
|
15:0 dma 0 instance address
|
|
|
|
31:16 dma 1 instance address
|
|
|
|
entry[3]
|
|
|
|
dma method traps
|
|
|
|
|
|
|
|
NV40:
|
|
|
|
No idea what the exact format is. Here's what can be deducted:
|
|
|
|
|
|
|
|
entry[0]:
|
|
|
|
11:0 class (maybe uses more bits here?)
|
|
|
|
17 user clip enable
|
|
|
|
21:19 patch config
|
|
|
|
25 patch status valid ?
|
|
|
|
entry[1]:
|
|
|
|
15:0 DMA notifier (maybe 20:0)
|
|
|
|
entry[2]:
|
|
|
|
15:0 DMA 0 instance (maybe 20:0)
|
|
|
|
24 big endian
|
|
|
|
entry[3]:
|
|
|
|
15:0 DMA 1 instance (maybe 20:0)
|
|
|
|
entry[4]:
|
|
|
|
entry[5]:
|
|
|
|
set to 0?
|
|
|
|
*/
|
2010-10-19 09:57:34 +00:00
|
|
|
static int
|
2011-03-31 03:44:16 +00:00
|
|
|
nouveau_gpuobj_sw_new(struct nouveau_channel *chan, u32 handle, u16 class)
|
2010-10-19 09:57:34 +00:00
|
|
|
{
|
2010-11-23 00:10:24 +00:00
|
|
|
struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
|
2010-10-19 09:57:34 +00:00
|
|
|
struct nouveau_gpuobj *gpuobj;
|
2011-03-31 03:44:16 +00:00
|
|
|
int ret;
|
2010-10-19 09:57:34 +00:00
|
|
|
|
|
|
|
gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
|
|
|
|
if (!gpuobj)
|
|
|
|
return -ENOMEM;
|
|
|
|
gpuobj->dev = chan->dev;
|
|
|
|
gpuobj->engine = NVOBJ_ENGINE_SW;
|
|
|
|
gpuobj->class = class;
|
|
|
|
kref_init(&gpuobj->refcount);
|
|
|
|
gpuobj->cinst = 0x40;
|
|
|
|
|
|
|
|
spin_lock(&dev_priv->ramin_lock);
|
|
|
|
list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
|
|
|
|
spin_unlock(&dev_priv->ramin_lock);
|
2011-03-31 03:44:16 +00:00
|
|
|
|
|
|
|
ret = nouveau_ramht_insert(chan, handle, gpuobj);
|
|
|
|
nouveau_gpuobj_ref(NULL, &gpuobj);
|
|
|
|
return ret;
|
2010-10-19 09:57:34 +00:00
|
|
|
}
|
|
|
|
|
2009-12-11 09:24:15 +00:00
|
|
|
int
|
2010-11-23 00:10:24 +00:00
|
|
|
nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class)
|
2009-12-11 09:24:15 +00:00
|
|
|
{
|
2010-10-19 09:57:34 +00:00
|
|
|
struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
|
2009-12-11 09:24:15 +00:00
|
|
|
struct drm_device *dev = chan->dev;
|
2010-10-20 00:39:35 +00:00
|
|
|
struct nouveau_gpuobj_class *oc;
|
2009-12-11 09:24:15 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class);
|
|
|
|
|
2010-10-20 00:39:35 +00:00
|
|
|
list_for_each_entry(oc, &dev_priv->classes, head) {
|
2011-04-01 03:56:05 +00:00
|
|
|
struct nouveau_exec_engine *eng = dev_priv->eng[oc->engine];
|
2010-10-19 09:57:34 +00:00
|
|
|
|
2011-04-01 03:56:05 +00:00
|
|
|
if (oc->id != class)
|
|
|
|
continue;
|
2010-10-19 09:57:34 +00:00
|
|
|
|
2011-04-01 03:56:05 +00:00
|
|
|
if (oc->engine == NVOBJ_ENGINE_SW)
|
2011-03-31 23:50:18 +00:00
|
|
|
return nouveau_gpuobj_sw_new(chan, handle, class);
|
2011-03-31 03:44:16 +00:00
|
|
|
|
2011-04-01 03:56:05 +00:00
|
|
|
if (!chan->engctx[oc->engine]) {
|
|
|
|
ret = eng->context_new(chan, oc->engine);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2011-03-31 23:50:18 +00:00
|
|
|
}
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2011-04-01 03:56:05 +00:00
|
|
|
return eng->object_new(chan, oc->engine, handle, class);
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
2010-11-23 00:10:24 +00:00
|
|
|
|
2011-04-01 03:56:05 +00:00
|
|
|
NV_ERROR(dev, "illegal object class: 0x%x\n", class);
|
|
|
|
return -EINVAL;
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = chan->dev;
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
uint32_t size;
|
|
|
|
uint32_t base;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
NV_DEBUG(dev, "ch%d\n", chan->id);
|
|
|
|
|
|
|
|
/* Base amount for object storage (4KiB enough?) */
|
2010-10-19 10:06:01 +00:00
|
|
|
size = 0x2000;
|
2009-12-11 09:24:15 +00:00
|
|
|
base = 0;
|
|
|
|
|
|
|
|
if (dev_priv->card_type == NV_50) {
|
|
|
|
/* Various fixed table thingos */
|
|
|
|
size += 0x1400; /* mostly unknown stuff */
|
|
|
|
size += 0x4000; /* vm pd */
|
|
|
|
base = 0x6000;
|
|
|
|
/* RAMHT, not sure about setting size yet, 32KiB to be safe */
|
|
|
|
size += 0x8000;
|
|
|
|
/* RAMFC */
|
|
|
|
size += 0x1000;
|
|
|
|
}
|
|
|
|
|
2010-09-01 05:24:31 +00:00
|
|
|
ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error allocating channel PRAMIN: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-09-01 05:24:30 +00:00
|
|
|
ret = drm_mm_init(&chan->ramin_heap, base, size);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error creating PRAMIN heap: %d\n", ret);
|
2010-09-01 05:24:31 +00:00
|
|
|
nouveau_gpuobj_ref(NULL, &chan->ramin);
|
2009-12-11 09:24:15 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-06-08 08:17:41 +00:00
|
|
|
static int
|
|
|
|
nvc0_gpuobj_channel_init(struct nouveau_channel *chan, struct nouveau_vm *vm)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = chan->dev;
|
|
|
|
struct nouveau_gpuobj *pgd = NULL;
|
|
|
|
struct nouveau_vm_pgd *vpgd;
|
|
|
|
int ret, i;
|
|
|
|
|
|
|
|
ret = nouveau_gpuobj_new(dev, NULL, 4096, 0x1000, 0, &chan->ramin);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* create page directory for this vm if none currently exists,
|
|
|
|
* will be destroyed automagically when last reference to the
|
|
|
|
* vm is removed
|
|
|
|
*/
|
|
|
|
if (list_empty(&vm->pgd_list)) {
|
|
|
|
ret = nouveau_gpuobj_new(dev, NULL, 65536, 0x1000, 0, &pgd);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
nouveau_vm_ref(vm, &chan->vm, pgd);
|
|
|
|
nouveau_gpuobj_ref(NULL, &pgd);
|
|
|
|
|
|
|
|
/* point channel at vm's page directory */
|
|
|
|
vpgd = list_first_entry(&vm->pgd_list, struct nouveau_vm_pgd, head);
|
|
|
|
nv_wo32(chan->ramin, 0x0200, lower_32_bits(vpgd->obj->vinst));
|
|
|
|
nv_wo32(chan->ramin, 0x0204, upper_32_bits(vpgd->obj->vinst));
|
|
|
|
nv_wo32(chan->ramin, 0x0208, 0xffffffff);
|
|
|
|
nv_wo32(chan->ramin, 0x020c, 0x000000ff);
|
|
|
|
|
|
|
|
/* map display semaphore buffers into channel's vm */
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
struct nv50_display_crtc *dispc = &nv50_display(dev)->crtc[i];
|
|
|
|
|
|
|
|
ret = nouveau_bo_vma_add(dispc->sem.bo, chan->vm,
|
|
|
|
&chan->dispc_vma[i]);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-12-11 09:24:15 +00:00
|
|
|
int
|
|
|
|
nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
|
|
|
|
uint32_t vram_h, uint32_t tt_h)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = chan->dev;
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
2011-06-03 00:20:52 +00:00
|
|
|
struct nouveau_fpriv *fpriv = nouveau_fpriv(chan->file_priv);
|
|
|
|
struct nouveau_vm *vm = fpriv ? fpriv->vm : dev_priv->chan_vm;
|
2009-12-11 09:24:15 +00:00
|
|
|
struct nouveau_gpuobj *vram = NULL, *tt = NULL;
|
2011-02-07 03:29:23 +00:00
|
|
|
int ret, i;
|
2009-12-11 09:24:15 +00:00
|
|
|
|
|
|
|
NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
|
2011-07-02 10:28:49 +00:00
|
|
|
if (dev_priv->card_type >= NV_C0)
|
2011-06-08 08:17:41 +00:00
|
|
|
return nvc0_gpuobj_channel_init(chan, vm);
|
2010-11-24 00:15:05 +00:00
|
|
|
|
2010-07-08 03:15:05 +00:00
|
|
|
/* Allocate a chunk of memory for per-channel object storage */
|
|
|
|
ret = nouveau_gpuobj_channel_init_pramin(chan);
|
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "init pramin\n");
|
|
|
|
return ret;
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
2010-11-24 00:15:05 +00:00
|
|
|
/* NV50 VM
|
2009-12-11 09:24:15 +00:00
|
|
|
* - Allocate per-channel page-directory
|
2010-11-15 01:54:21 +00:00
|
|
|
* - Link with shared channel VM
|
2009-12-11 09:24:15 +00:00
|
|
|
*/
|
2011-06-03 00:20:52 +00:00
|
|
|
if (vm) {
|
2010-09-01 05:24:33 +00:00
|
|
|
u32 pgd_offs = (dev_priv->chipset == 0x50) ? 0x1400 : 0x0200;
|
|
|
|
u64 vm_vinst = chan->ramin->vinst + pgd_offs;
|
|
|
|
u32 vm_pinst = chan->ramin->pinst;
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-09-01 05:24:33 +00:00
|
|
|
if (vm_pinst != ~0)
|
|
|
|
vm_pinst += pgd_offs;
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-09-01 05:24:33 +00:00
|
|
|
ret = nouveau_gpuobj_new_fake(dev, vm_pinst, vm_vinst, 0x4000,
|
2010-09-01 05:24:31 +00:00
|
|
|
0, &chan->vm_pd);
|
2010-07-08 01:29:10 +00:00
|
|
|
if (ret)
|
2009-12-11 09:24:15 +00:00
|
|
|
return ret;
|
|
|
|
|
2011-06-03 00:20:52 +00:00
|
|
|
nouveau_vm_ref(vm, &chan->vm, chan->vm_pd);
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* RAMHT */
|
|
|
|
if (dev_priv->card_type < NV_50) {
|
2010-09-01 05:24:31 +00:00
|
|
|
nouveau_ramht_ref(dev_priv->ramht, &chan->ramht, NULL);
|
|
|
|
} else {
|
|
|
|
struct nouveau_gpuobj *ramht = NULL;
|
|
|
|
|
|
|
|
ret = nouveau_gpuobj_new(dev, chan, 0x8000, 16,
|
|
|
|
NVOBJ_FLAG_ZERO_ALLOC, &ramht);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2010-09-01 05:24:31 +00:00
|
|
|
|
|
|
|
ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
|
|
|
|
nouveau_gpuobj_ref(NULL, &ramht);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2011-02-07 03:29:23 +00:00
|
|
|
|
|
|
|
/* dma objects for display sync channel semaphore blocks */
|
2011-07-04 01:55:39 +00:00
|
|
|
for (i = 0; i < dev->mode_config.num_crtc; i++) {
|
2011-02-07 03:29:23 +00:00
|
|
|
struct nouveau_gpuobj *sem = NULL;
|
|
|
|
struct nv50_display_crtc *dispc =
|
|
|
|
&nv50_display(dev)->crtc[i];
|
2011-06-07 01:24:14 +00:00
|
|
|
u64 offset = dispc->sem.bo->bo.offset;
|
2011-02-07 03:29:23 +00:00
|
|
|
|
|
|
|
ret = nouveau_gpuobj_dma_new(chan, 0x3d, offset, 0xfff,
|
|
|
|
NV_MEM_ACCESS_RW,
|
|
|
|
NV_MEM_TARGET_VRAM, &sem);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = nouveau_ramht_insert(chan, NvEvoSema0 + i, sem);
|
|
|
|
nouveau_gpuobj_ref(NULL, &sem);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* VRAM ctxdma */
|
|
|
|
if (dev_priv->card_type >= NV_50) {
|
|
|
|
ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
|
2010-11-15 01:54:21 +00:00
|
|
|
0, (1ULL << 40), NV_MEM_ACCESS_RW,
|
2010-11-16 01:50:09 +00:00
|
|
|
NV_MEM_TARGET_VM, &vram);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
|
2010-09-01 05:24:31 +00:00
|
|
|
0, dev_priv->fb_available_size,
|
2010-11-16 01:50:09 +00:00
|
|
|
NV_MEM_ACCESS_RW,
|
|
|
|
NV_MEM_TARGET_VRAM, &vram);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-09-01 05:24:31 +00:00
|
|
|
ret = nouveau_ramht_insert(chan, vram_h, vram);
|
|
|
|
nouveau_gpuobj_ref(NULL, &vram);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret) {
|
2010-09-01 05:24:31 +00:00
|
|
|
NV_ERROR(dev, "Error adding VRAM ctxdma to RAMHT: %d\n", ret);
|
2009-12-11 09:24:15 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* TT memory ctxdma */
|
|
|
|
if (dev_priv->card_type >= NV_50) {
|
2010-09-01 05:24:31 +00:00
|
|
|
ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
|
2010-11-15 01:54:21 +00:00
|
|
|
0, (1ULL << 40), NV_MEM_ACCESS_RW,
|
2010-11-16 01:50:09 +00:00
|
|
|
NV_MEM_TARGET_VM, &tt);
|
2009-12-11 09:24:15 +00:00
|
|
|
} else {
|
2010-11-16 01:50:09 +00:00
|
|
|
ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
|
|
|
|
0, dev_priv->gart_info.aper_size,
|
|
|
|
NV_MEM_ACCESS_RW,
|
|
|
|
NV_MEM_TARGET_GART, &tt);
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error creating TT ctxdma: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-09-01 05:24:31 +00:00
|
|
|
ret = nouveau_ramht_insert(chan, tt_h, tt);
|
|
|
|
nouveau_gpuobj_ref(NULL, &tt);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret) {
|
2010-09-01 05:24:31 +00:00
|
|
|
NV_ERROR(dev, "Error adding TT ctxdma to RAMHT: %d\n", ret);
|
2009-12-11 09:24:15 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = chan->dev;
|
2011-06-13 02:23:35 +00:00
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
2011-06-07 05:43:31 +00:00
|
|
|
int i;
|
2009-12-11 09:24:15 +00:00
|
|
|
|
|
|
|
NV_DEBUG(dev, "ch%d\n", chan->id);
|
|
|
|
|
2011-06-13 02:23:35 +00:00
|
|
|
if (dev_priv->card_type >= NV_50) {
|
|
|
|
struct nv50_display *disp = nv50_display(dev);
|
|
|
|
|
2011-07-04 01:55:39 +00:00
|
|
|
for (i = 0; i < dev->mode_config.num_crtc; i++) {
|
2011-06-13 02:23:35 +00:00
|
|
|
struct nv50_display_crtc *dispc = &disp->crtc[i];
|
|
|
|
nouveau_bo_vma_del(dispc->sem.bo, &chan->dispc_vma[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
nouveau_vm_ref(NULL, &chan->vm, chan->vm_pd);
|
|
|
|
nouveau_gpuobj_ref(NULL, &chan->vm_pd);
|
2011-06-07 05:43:31 +00:00
|
|
|
}
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2011-02-18 16:59:11 +00:00
|
|
|
if (drm_mm_initialized(&chan->ramin_heap))
|
2010-06-01 05:32:24 +00:00
|
|
|
drm_mm_takedown(&chan->ramin_heap);
|
2010-09-01 05:24:31 +00:00
|
|
|
nouveau_gpuobj_ref(NULL, &chan->ramin);
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
nouveau_gpuobj_suspend(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
struct nouveau_gpuobj *gpuobj;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
|
2010-11-01 01:45:02 +00:00
|
|
|
if (gpuobj->cinst != NVOBJ_CINST_GLOBAL)
|
2009-12-11 09:24:15 +00:00
|
|
|
continue;
|
|
|
|
|
2010-10-25 05:23:59 +00:00
|
|
|
gpuobj->suspend = vmalloc(gpuobj->size);
|
|
|
|
if (!gpuobj->suspend) {
|
2009-12-11 09:24:15 +00:00
|
|
|
nouveau_gpuobj_resume(dev);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2010-09-01 05:24:32 +00:00
|
|
|
for (i = 0; i < gpuobj->size; i += 4)
|
2010-10-25 05:23:59 +00:00
|
|
|
gpuobj->suspend[i/4] = nv_ro32(gpuobj, i);
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
nouveau_gpuobj_resume(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
struct nouveau_gpuobj *gpuobj;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
|
2010-10-25 05:23:59 +00:00
|
|
|
if (!gpuobj->suspend)
|
2009-12-11 09:24:15 +00:00
|
|
|
continue;
|
|
|
|
|
2010-09-01 05:24:32 +00:00
|
|
|
for (i = 0; i < gpuobj->size; i += 4)
|
2010-10-25 05:23:59 +00:00
|
|
|
nv_wo32(gpuobj, i, gpuobj->suspend[i/4]);
|
|
|
|
|
|
|
|
vfree(gpuobj->suspend);
|
|
|
|
gpuobj->suspend = NULL;
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
2010-10-25 05:23:59 +00:00
|
|
|
dev_priv->engine.instmem.flush(dev);
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv)
|
|
|
|
{
|
|
|
|
struct drm_nouveau_grobj_alloc *init = data;
|
|
|
|
struct nouveau_channel *chan;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (init->handle == ~0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2011-06-01 09:18:48 +00:00
|
|
|
chan = nouveau_channel_get(file_priv, init->channel);
|
2010-10-06 06:16:59 +00:00
|
|
|
if (IS_ERR(chan))
|
|
|
|
return PTR_ERR(chan);
|
|
|
|
|
|
|
|
if (nouveau_ramht_find(chan, init->handle)) {
|
|
|
|
ret = -EEXIST;
|
|
|
|
goto out;
|
|
|
|
}
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-11-23 00:10:24 +00:00
|
|
|
ret = nouveau_gpuobj_gr_new(chan, init->handle, init->class);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n",
|
|
|
|
ret, init->channel, init->handle);
|
|
|
|
}
|
|
|
|
|
2010-10-06 06:16:59 +00:00
|
|
|
out:
|
|
|
|
nouveau_channel_put(&chan);
|
|
|
|
return ret;
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv)
|
|
|
|
{
|
|
|
|
struct drm_nouveau_gpuobj_free *objfree = data;
|
|
|
|
struct nouveau_channel *chan;
|
2010-10-12 00:11:00 +00:00
|
|
|
int ret;
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2011-06-01 09:18:48 +00:00
|
|
|
chan = nouveau_channel_get(file_priv, objfree->channel);
|
2010-10-06 06:16:59 +00:00
|
|
|
if (IS_ERR(chan))
|
|
|
|
return PTR_ERR(chan);
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-11-18 22:57:46 +00:00
|
|
|
/* Synchronize with the user channel */
|
|
|
|
nouveau_channel_idle(chan);
|
|
|
|
|
2010-10-12 00:11:00 +00:00
|
|
|
ret = nouveau_ramht_remove(chan, objfree->handle);
|
2010-10-06 06:16:59 +00:00
|
|
|
nouveau_channel_put(&chan);
|
|
|
|
return ret;
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
2010-09-01 05:24:29 +00:00
|
|
|
|
|
|
|
u32
|
|
|
|
nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset)
|
|
|
|
{
|
2010-09-01 05:24:33 +00:00
|
|
|
struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
|
|
|
|
struct drm_device *dev = gpuobj->dev;
|
2011-04-06 03:28:35 +00:00
|
|
|
unsigned long flags;
|
2010-09-01 05:24:33 +00:00
|
|
|
|
|
|
|
if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
|
|
|
|
u64 ptr = gpuobj->vinst + offset;
|
|
|
|
u32 base = ptr >> 16;
|
|
|
|
u32 val;
|
|
|
|
|
2011-04-06 03:28:35 +00:00
|
|
|
spin_lock_irqsave(&dev_priv->vm_lock, flags);
|
2010-09-01 05:24:33 +00:00
|
|
|
if (dev_priv->ramin_base != base) {
|
|
|
|
dev_priv->ramin_base = base;
|
|
|
|
nv_wr32(dev, 0x001700, dev_priv->ramin_base);
|
|
|
|
}
|
|
|
|
val = nv_rd32(dev, 0x700000 + (ptr & 0xffff));
|
2011-04-06 03:28:35 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->vm_lock, flags);
|
2010-09-01 05:24:33 +00:00
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
return nv_ri32(dev, gpuobj->pinst + offset);
|
2010-09-01 05:24:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
nv_wo32(struct nouveau_gpuobj *gpuobj, u32 offset, u32 val)
|
|
|
|
{
|
2010-09-01 05:24:33 +00:00
|
|
|
struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
|
|
|
|
struct drm_device *dev = gpuobj->dev;
|
2011-04-06 03:28:35 +00:00
|
|
|
unsigned long flags;
|
2010-09-01 05:24:33 +00:00
|
|
|
|
|
|
|
if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
|
|
|
|
u64 ptr = gpuobj->vinst + offset;
|
|
|
|
u32 base = ptr >> 16;
|
|
|
|
|
2011-04-06 03:28:35 +00:00
|
|
|
spin_lock_irqsave(&dev_priv->vm_lock, flags);
|
2010-09-01 05:24:33 +00:00
|
|
|
if (dev_priv->ramin_base != base) {
|
|
|
|
dev_priv->ramin_base = base;
|
|
|
|
nv_wr32(dev, 0x001700, dev_priv->ramin_base);
|
|
|
|
}
|
|
|
|
nv_wr32(dev, 0x700000 + (ptr & 0xffff), val);
|
2011-04-06 03:28:35 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->vm_lock, flags);
|
2010-09-01 05:24:33 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
nv_wi32(dev, gpuobj->pinst + offset, val);
|
2010-09-01 05:24:29 +00:00
|
|
|
}
|