2009-12-11 09:24:15 +00:00
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/*
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* Copyright (C) 2006 Ben Skeggs.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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/*
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* Authors:
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* Ben Skeggs <darktama@iinet.net.au>
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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2010-09-01 05:24:28 +00:00
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#include "nouveau_ramht.h"
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2009-12-11 09:24:15 +00:00
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/* NVidia uses context objects to drive drawing operations.
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Context objects can be selected into 8 subchannels in the FIFO,
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and then used via DMA command buffers.
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A context object is referenced by a user defined handle (CARD32). The HW
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looks up graphics objects in a hash table in the instance RAM.
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An entry in the hash table consists of 2 CARD32. The first CARD32 contains
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the handle, the second one a bitfield, that contains the address of the
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object in instance RAM.
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The format of the second CARD32 seems to be:
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NV4 to NV30:
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15: 0 instance_addr >> 4
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17:16 engine (here uses 1 = graphics)
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28:24 channel id (here uses 0)
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31 valid (use 1)
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NV40:
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15: 0 instance_addr >> 4 (maybe 19-0)
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21:20 engine (here uses 1 = graphics)
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I'm unsure about the other bits, but using 0 seems to work.
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The key into the hash table depends on the object handle and channel id and
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is given as:
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*/
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int
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nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
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uint32_t size, int align, uint32_t flags,
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struct nouveau_gpuobj **gpuobj_ret)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_engine *engine = &dev_priv->engine;
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struct nouveau_gpuobj *gpuobj;
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2010-09-01 05:24:33 +00:00
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struct drm_mm_node *ramin = NULL;
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2009-12-11 09:24:15 +00:00
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int ret;
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NV_DEBUG(dev, "ch%d size=%u align=%d flags=0x%08x\n",
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chan ? chan->id : -1, size, align, flags);
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if (!dev_priv || !gpuobj_ret || *gpuobj_ret != NULL)
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return -EINVAL;
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gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
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if (!gpuobj)
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return -ENOMEM;
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NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
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2010-09-01 05:24:29 +00:00
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gpuobj->dev = dev;
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2009-12-11 09:24:15 +00:00
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gpuobj->flags = flags;
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2010-09-01 05:24:31 +00:00
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gpuobj->refcount = 1;
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2010-09-01 05:24:32 +00:00
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gpuobj->size = size;
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2009-12-11 09:24:15 +00:00
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list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
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if (chan) {
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2010-07-08 03:15:05 +00:00
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NV_DEBUG(dev, "channel heap\n");
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2010-09-01 05:24:33 +00:00
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ramin = drm_mm_search_free(&chan->ramin_heap, size, align, 0);
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if (ramin)
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ramin = drm_mm_get_block(ramin, size, align);
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if (!ramin) {
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nouveau_gpuobj_ref(NULL, &gpuobj);
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return -ENOMEM;
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}
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2009-12-11 09:24:15 +00:00
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} else {
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NV_DEBUG(dev, "global heap\n");
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2010-09-01 05:24:33 +00:00
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/* allocate backing pages, sets vinst */
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2009-12-11 09:24:15 +00:00
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ret = engine->instmem.populate(dev, gpuobj, &size);
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if (ret) {
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2010-09-01 05:24:31 +00:00
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nouveau_gpuobj_ref(NULL, &gpuobj);
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2009-12-11 09:24:15 +00:00
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return ret;
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}
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2010-09-01 05:24:33 +00:00
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/* try and get aperture space */
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ramin = drm_mm_search_free(&dev_priv->ramin_heap, size, align, 0);
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if (ramin)
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ramin = drm_mm_get_block(ramin, size, align);
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2010-06-01 05:32:24 +00:00
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2010-09-01 05:24:33 +00:00
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/* on nv50 it's ok to fail, we have a fallback path */
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if (!ramin && dev_priv->card_type < NV_50) {
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nouveau_gpuobj_ref(NULL, &gpuobj);
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return -ENOMEM;
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}
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2009-12-11 09:24:15 +00:00
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}
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2010-09-01 05:24:33 +00:00
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/* if we got a chunk of the aperture, map pages into it */
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gpuobj->im_pramin = ramin;
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2010-09-01 05:24:34 +00:00
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if (!chan && gpuobj->im_pramin && dev_priv->ramin_available) {
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2009-12-11 09:24:15 +00:00
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ret = engine->instmem.bind(dev, gpuobj);
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if (ret) {
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2010-09-01 05:24:31 +00:00
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nouveau_gpuobj_ref(NULL, &gpuobj);
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2009-12-11 09:24:15 +00:00
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return ret;
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}
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}
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2010-09-01 05:24:30 +00:00
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/* calculate the various different addresses for the object */
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if (chan) {
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2010-09-01 05:24:33 +00:00
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gpuobj->pinst = chan->ramin->pinst;
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if (gpuobj->pinst != ~0)
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gpuobj->pinst += gpuobj->im_pramin->start;
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2010-09-01 05:24:30 +00:00
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if (dev_priv->card_type < NV_50) {
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gpuobj->cinst = gpuobj->pinst;
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} else {
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gpuobj->cinst = gpuobj->im_pramin->start;
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gpuobj->vinst = gpuobj->im_pramin->start +
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2010-09-01 05:24:32 +00:00
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chan->ramin->vinst;
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2010-09-01 05:24:30 +00:00
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}
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} else {
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2010-09-01 05:24:33 +00:00
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if (gpuobj->im_pramin)
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gpuobj->pinst = gpuobj->im_pramin->start;
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else
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gpuobj->pinst = ~0;
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2010-09-01 05:24:30 +00:00
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gpuobj->cinst = 0xdeadbeef;
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}
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2009-12-11 09:24:15 +00:00
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if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
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int i;
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2010-09-01 05:24:32 +00:00
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for (i = 0; i < gpuobj->size; i += 4)
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2010-09-01 05:24:29 +00:00
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nv_wo32(gpuobj, i, 0);
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2010-07-08 01:29:10 +00:00
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engine->instmem.flush(dev);
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2009-12-11 09:24:15 +00:00
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}
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2010-09-01 05:24:31 +00:00
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2009-12-11 09:24:15 +00:00
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*gpuobj_ret = gpuobj;
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return 0;
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}
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int
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2010-09-01 05:24:34 +00:00
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nouveau_gpuobj_init(struct drm_device *dev)
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2009-12-11 09:24:15 +00:00
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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NV_DEBUG(dev, "\n");
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INIT_LIST_HEAD(&dev_priv->gpuobj_list);
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2010-09-01 05:24:33 +00:00
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spin_lock_init(&dev_priv->ramin_lock);
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dev_priv->ramin_base = ~0;
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2009-12-11 09:24:15 +00:00
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return 0;
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}
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void
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nouveau_gpuobj_takedown(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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NV_DEBUG(dev, "\n");
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}
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void
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nouveau_gpuobj_late_takedown(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gpuobj = NULL;
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struct list_head *entry, *tmp;
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NV_DEBUG(dev, "\n");
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list_for_each_safe(entry, tmp, &dev_priv->gpuobj_list) {
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gpuobj = list_entry(entry, struct nouveau_gpuobj, list);
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NV_ERROR(dev, "gpuobj %p still exists at takedown, refs=%d\n",
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gpuobj, gpuobj->refcount);
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2010-09-01 05:24:31 +00:00
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gpuobj->refcount = 1;
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nouveau_gpuobj_ref(NULL, &gpuobj);
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2009-12-11 09:24:15 +00:00
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}
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}
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2010-09-01 05:24:31 +00:00
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static int
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nouveau_gpuobj_del(struct nouveau_gpuobj *gpuobj)
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2009-12-11 09:24:15 +00:00
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{
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2010-09-01 05:24:31 +00:00
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struct drm_device *dev = gpuobj->dev;
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2009-12-11 09:24:15 +00:00
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_engine *engine = &dev_priv->engine;
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int i;
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2010-09-01 05:24:31 +00:00
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NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
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2009-12-11 09:24:15 +00:00
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if (gpuobj->im_pramin && (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE)) {
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2010-09-01 05:24:32 +00:00
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for (i = 0; i < gpuobj->size; i += 4)
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2010-09-01 05:24:29 +00:00
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nv_wo32(gpuobj, i, 0);
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2010-07-08 01:29:10 +00:00
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engine->instmem.flush(dev);
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2009-12-11 09:24:15 +00:00
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}
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if (gpuobj->dtor)
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gpuobj->dtor(dev, gpuobj);
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2010-09-01 05:24:32 +00:00
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if (gpuobj->im_backing)
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2009-12-11 09:24:15 +00:00
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engine->instmem.clear(dev, gpuobj);
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2010-09-01 05:24:32 +00:00
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if (gpuobj->im_pramin)
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drm_mm_put_block(gpuobj->im_pramin);
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2009-12-11 09:24:15 +00:00
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list_del(&gpuobj->list);
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kfree(gpuobj);
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return 0;
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}
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2010-09-01 05:24:31 +00:00
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void
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nouveau_gpuobj_ref(struct nouveau_gpuobj *ref, struct nouveau_gpuobj **ptr)
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2009-12-11 09:24:15 +00:00
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{
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2010-09-01 05:24:31 +00:00
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if (ref)
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ref->refcount++;
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2009-12-11 09:24:15 +00:00
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2010-09-01 05:24:31 +00:00
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if (*ptr && --(*ptr)->refcount == 0)
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nouveau_gpuobj_del(*ptr);
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2009-12-11 09:24:15 +00:00
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2010-09-01 05:24:31 +00:00
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*ptr = ref;
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2009-12-11 09:24:15 +00:00
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}
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int
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2010-09-01 05:24:32 +00:00
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nouveau_gpuobj_new_fake(struct drm_device *dev, u32 pinst, u64 vinst,
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u32 size, u32 flags, struct nouveau_gpuobj **pgpuobj)
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2009-12-11 09:24:15 +00:00
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gpuobj = NULL;
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int i;
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NV_DEBUG(dev,
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2010-09-01 05:24:32 +00:00
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"pinst=0x%08x vinst=0x%010llx size=0x%08x flags=0x%08x\n",
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pinst, vinst, size, flags);
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2009-12-11 09:24:15 +00:00
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gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
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if (!gpuobj)
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return -ENOMEM;
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NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
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2010-09-01 05:24:29 +00:00
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gpuobj->dev = dev;
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2010-09-01 05:24:32 +00:00
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gpuobj->flags = flags;
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2010-09-01 05:24:31 +00:00
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gpuobj->refcount = 1;
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2010-09-01 05:24:32 +00:00
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gpuobj->size = size;
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gpuobj->pinst = pinst;
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2010-09-01 05:24:30 +00:00
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gpuobj->cinst = 0xdeadbeef;
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2010-09-01 05:24:32 +00:00
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gpuobj->vinst = vinst;
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2010-09-01 05:24:30 +00:00
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2009-12-11 09:24:15 +00:00
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if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
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2010-09-01 05:24:32 +00:00
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for (i = 0; i < gpuobj->size; i += 4)
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2010-09-01 05:24:29 +00:00
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nv_wo32(gpuobj, i, 0);
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2010-07-08 01:29:10 +00:00
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dev_priv->engine.instmem.flush(dev);
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2009-12-11 09:24:15 +00:00
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}
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2010-09-01 05:24:32 +00:00
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list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
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*pgpuobj = gpuobj;
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2009-12-11 09:24:15 +00:00
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return 0;
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}
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static uint32_t
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nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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/*XXX: dodgy hack for now */
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if (dev_priv->card_type >= NV_50)
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return 24;
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if (dev_priv->card_type >= NV_40)
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return 32;
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return 16;
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}
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/*
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DMA objects are used to reference a piece of memory in the
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framebuffer, PCI or AGP address space. Each object is 16 bytes big
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and looks as follows:
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entry[0]
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|
|
11:0 class (seems like I can always use 0 here)
|
|
|
|
12 page table present?
|
|
|
|
13 page entry linear?
|
|
|
|
15:14 access: 0 rw, 1 ro, 2 wo
|
|
|
|
17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP
|
|
|
|
31:20 dma adjust (bits 0-11 of the address)
|
|
|
|
entry[1]
|
|
|
|
dma limit (size of transfer)
|
|
|
|
entry[X]
|
|
|
|
1 0 readonly, 1 readwrite
|
|
|
|
31:12 dma frame address of the page (bits 12-31 of the address)
|
|
|
|
entry[N]
|
|
|
|
page table terminator, same value as the first pte, as does nvidia
|
|
|
|
rivatv uses 0xffffffff
|
|
|
|
|
|
|
|
Non linear page tables need a list of frame addresses afterwards,
|
|
|
|
the rivatv project has some info on this.
|
|
|
|
|
|
|
|
The method below creates a DMA object in instance RAM and returns a handle
|
|
|
|
to it that can be used to set up context objects.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class,
|
|
|
|
uint64_t offset, uint64_t size, int access,
|
|
|
|
int target, struct nouveau_gpuobj **gpuobj)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = chan->dev;
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
NV_DEBUG(dev, "ch%d class=0x%04x offset=0x%llx size=0x%llx\n",
|
|
|
|
chan->id, class, offset, size);
|
|
|
|
NV_DEBUG(dev, "access=%d target=%d\n", access, target);
|
|
|
|
|
|
|
|
switch (target) {
|
|
|
|
case NV_DMA_TARGET_AGP:
|
|
|
|
offset += dev_priv->gart_info.aper_base;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = nouveau_gpuobj_new(dev, chan,
|
|
|
|
nouveau_gpuobj_class_instmem_size(dev, class),
|
|
|
|
16, NVOBJ_FLAG_ZERO_ALLOC |
|
|
|
|
NVOBJ_FLAG_ZERO_FREE, gpuobj);
|
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error creating gpuobj: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev_priv->card_type < NV_50) {
|
|
|
|
uint32_t frame, adjust, pte_flags = 0;
|
|
|
|
|
|
|
|
if (access != NV_DMA_ACCESS_RO)
|
|
|
|
pte_flags |= (1<<1);
|
|
|
|
adjust = offset & 0x00000fff;
|
|
|
|
frame = offset & ~0x00000fff;
|
|
|
|
|
2010-09-01 05:24:29 +00:00
|
|
|
nv_wo32(*gpuobj, 0, ((1<<12) | (1<<13) | (adjust << 20) |
|
|
|
|
(access << 14) | (target << 16) |
|
|
|
|
class));
|
|
|
|
nv_wo32(*gpuobj, 4, size - 1);
|
|
|
|
nv_wo32(*gpuobj, 8, frame | pte_flags);
|
|
|
|
nv_wo32(*gpuobj, 12, frame | pte_flags);
|
2009-12-11 09:24:15 +00:00
|
|
|
} else {
|
|
|
|
uint64_t limit = offset + size - 1;
|
|
|
|
uint32_t flags0, flags5;
|
|
|
|
|
|
|
|
if (target == NV_DMA_TARGET_VIDMEM) {
|
|
|
|
flags0 = 0x00190000;
|
|
|
|
flags5 = 0x00010000;
|
|
|
|
} else {
|
|
|
|
flags0 = 0x7fc00000;
|
|
|
|
flags5 = 0x00080000;
|
|
|
|
}
|
|
|
|
|
2010-09-01 05:24:29 +00:00
|
|
|
nv_wo32(*gpuobj, 0, flags0 | class);
|
|
|
|
nv_wo32(*gpuobj, 4, lower_32_bits(limit));
|
|
|
|
nv_wo32(*gpuobj, 8, lower_32_bits(offset));
|
|
|
|
nv_wo32(*gpuobj, 12, ((upper_32_bits(limit) & 0xff) << 24) |
|
|
|
|
(upper_32_bits(offset) & 0xff));
|
|
|
|
nv_wo32(*gpuobj, 20, flags5);
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
2010-07-08 01:29:10 +00:00
|
|
|
instmem->flush(dev);
|
2009-12-11 09:24:15 +00:00
|
|
|
|
|
|
|
(*gpuobj)->engine = NVOBJ_ENGINE_SW;
|
|
|
|
(*gpuobj)->class = class;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
nouveau_gpuobj_gart_dma_new(struct nouveau_channel *chan,
|
|
|
|
uint64_t offset, uint64_t size, int access,
|
|
|
|
struct nouveau_gpuobj **gpuobj,
|
|
|
|
uint32_t *o_ret)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = chan->dev;
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (dev_priv->gart_info.type == NOUVEAU_GART_AGP ||
|
|
|
|
(dev_priv->card_type >= NV_50 &&
|
|
|
|
dev_priv->gart_info.type == NOUVEAU_GART_SGDMA)) {
|
|
|
|
ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
|
|
|
|
offset + dev_priv->vm_gart_base,
|
|
|
|
size, access, NV_DMA_TARGET_AGP,
|
|
|
|
gpuobj);
|
|
|
|
if (o_ret)
|
|
|
|
*o_ret = 0;
|
|
|
|
} else
|
|
|
|
if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA) {
|
2010-09-01 05:24:31 +00:00
|
|
|
nouveau_gpuobj_ref(dev_priv->gart_info.sg_ctxdma, gpuobj);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (offset & ~0xffffffffULL) {
|
|
|
|
NV_ERROR(dev, "obj offset exceeds 32-bits\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
if (o_ret)
|
|
|
|
*o_ret = (uint32_t)offset;
|
|
|
|
ret = (*gpuobj != NULL) ? 0 : -EINVAL;
|
|
|
|
} else {
|
|
|
|
NV_ERROR(dev, "Invalid GART type %d\n", dev_priv->gart_info.type);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Context objects in the instance RAM have the following structure.
|
|
|
|
* On NV40 they are 32 byte long, on NV30 and smaller 16 bytes.
|
|
|
|
|
|
|
|
NV4 - NV30:
|
|
|
|
|
|
|
|
entry[0]
|
|
|
|
11:0 class
|
|
|
|
12 chroma key enable
|
|
|
|
13 user clip enable
|
|
|
|
14 swizzle enable
|
|
|
|
17:15 patch config:
|
|
|
|
scrcopy_and, rop_and, blend_and, scrcopy, srccopy_pre, blend_pre
|
|
|
|
18 synchronize enable
|
|
|
|
19 endian: 1 big, 0 little
|
|
|
|
21:20 dither mode
|
|
|
|
23 single step enable
|
|
|
|
24 patch status: 0 invalid, 1 valid
|
|
|
|
25 context_surface 0: 1 valid
|
|
|
|
26 context surface 1: 1 valid
|
|
|
|
27 context pattern: 1 valid
|
|
|
|
28 context rop: 1 valid
|
|
|
|
29,30 context beta, beta4
|
|
|
|
entry[1]
|
|
|
|
7:0 mono format
|
|
|
|
15:8 color format
|
|
|
|
31:16 notify instance address
|
|
|
|
entry[2]
|
|
|
|
15:0 dma 0 instance address
|
|
|
|
31:16 dma 1 instance address
|
|
|
|
entry[3]
|
|
|
|
dma method traps
|
|
|
|
|
|
|
|
NV40:
|
|
|
|
No idea what the exact format is. Here's what can be deducted:
|
|
|
|
|
|
|
|
entry[0]:
|
|
|
|
11:0 class (maybe uses more bits here?)
|
|
|
|
17 user clip enable
|
|
|
|
21:19 patch config
|
|
|
|
25 patch status valid ?
|
|
|
|
entry[1]:
|
|
|
|
15:0 DMA notifier (maybe 20:0)
|
|
|
|
entry[2]:
|
|
|
|
15:0 DMA 0 instance (maybe 20:0)
|
|
|
|
24 big endian
|
|
|
|
entry[3]:
|
|
|
|
15:0 DMA 1 instance (maybe 20:0)
|
|
|
|
entry[4]:
|
|
|
|
entry[5]:
|
|
|
|
set to 0?
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class,
|
|
|
|
struct nouveau_gpuobj **gpuobj)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = chan->dev;
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class);
|
|
|
|
|
|
|
|
ret = nouveau_gpuobj_new(dev, chan,
|
|
|
|
nouveau_gpuobj_class_instmem_size(dev, class),
|
|
|
|
16,
|
|
|
|
NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
|
|
|
|
gpuobj);
|
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error creating gpuobj: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev_priv->card_type >= NV_50) {
|
2010-09-01 05:24:29 +00:00
|
|
|
nv_wo32(*gpuobj, 0, class);
|
|
|
|
nv_wo32(*gpuobj, 20, 0x00010000);
|
2009-12-11 09:24:15 +00:00
|
|
|
} else {
|
|
|
|
switch (class) {
|
|
|
|
case NV_CLASS_NULL:
|
2010-09-01 05:24:29 +00:00
|
|
|
nv_wo32(*gpuobj, 0, 0x00001030);
|
|
|
|
nv_wo32(*gpuobj, 4, 0xFFFFFFFF);
|
2009-12-11 09:24:15 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
if (dev_priv->card_type >= NV_40) {
|
2010-09-01 05:24:29 +00:00
|
|
|
nv_wo32(*gpuobj, 0, class);
|
2009-12-11 09:24:15 +00:00
|
|
|
#ifdef __BIG_ENDIAN
|
2010-09-01 05:24:29 +00:00
|
|
|
nv_wo32(*gpuobj, 8, 0x01000000);
|
2009-12-11 09:24:15 +00:00
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
#ifdef __BIG_ENDIAN
|
2010-09-01 05:24:29 +00:00
|
|
|
nv_wo32(*gpuobj, 0, class | 0x00080000);
|
2009-12-11 09:24:15 +00:00
|
|
|
#else
|
2010-09-01 05:24:29 +00:00
|
|
|
nv_wo32(*gpuobj, 0, class);
|
2009-12-11 09:24:15 +00:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2010-07-08 01:29:10 +00:00
|
|
|
dev_priv->engine.instmem.flush(dev);
|
2009-12-11 09:24:15 +00:00
|
|
|
|
|
|
|
(*gpuobj)->engine = NVOBJ_ENGINE_GR;
|
|
|
|
(*gpuobj)->class = class;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-12-26 01:42:45 +00:00
|
|
|
int
|
2009-12-11 09:24:15 +00:00
|
|
|
nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class,
|
|
|
|
struct nouveau_gpuobj **gpuobj_ret)
|
|
|
|
{
|
2010-01-30 14:41:00 +00:00
|
|
|
struct drm_nouveau_private *dev_priv;
|
2009-12-11 09:24:15 +00:00
|
|
|
struct nouveau_gpuobj *gpuobj;
|
|
|
|
|
|
|
|
if (!chan || !gpuobj_ret || *gpuobj_ret != NULL)
|
|
|
|
return -EINVAL;
|
2010-01-30 14:41:00 +00:00
|
|
|
dev_priv = chan->dev->dev_private;
|
2009-12-11 09:24:15 +00:00
|
|
|
|
|
|
|
gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
|
|
|
|
if (!gpuobj)
|
|
|
|
return -ENOMEM;
|
2010-09-01 05:24:31 +00:00
|
|
|
gpuobj->dev = chan->dev;
|
2009-12-11 09:24:15 +00:00
|
|
|
gpuobj->engine = NVOBJ_ENGINE_SW;
|
|
|
|
gpuobj->class = class;
|
2010-09-01 05:24:31 +00:00
|
|
|
gpuobj->refcount = 1;
|
|
|
|
gpuobj->cinst = 0x40;
|
2009-12-11 09:24:15 +00:00
|
|
|
|
|
|
|
list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
|
|
|
|
*gpuobj_ret = gpuobj;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = chan->dev;
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
uint32_t size;
|
|
|
|
uint32_t base;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
NV_DEBUG(dev, "ch%d\n", chan->id);
|
|
|
|
|
|
|
|
/* Base amount for object storage (4KiB enough?) */
|
|
|
|
size = 0x1000;
|
|
|
|
base = 0;
|
|
|
|
|
|
|
|
/* PGRAPH context */
|
2010-07-08 03:15:05 +00:00
|
|
|
size += dev_priv->engine.graph.grctx_size;
|
2009-12-11 09:24:15 +00:00
|
|
|
|
|
|
|
if (dev_priv->card_type == NV_50) {
|
|
|
|
/* Various fixed table thingos */
|
|
|
|
size += 0x1400; /* mostly unknown stuff */
|
|
|
|
size += 0x4000; /* vm pd */
|
|
|
|
base = 0x6000;
|
|
|
|
/* RAMHT, not sure about setting size yet, 32KiB to be safe */
|
|
|
|
size += 0x8000;
|
|
|
|
/* RAMFC */
|
|
|
|
size += 0x1000;
|
|
|
|
}
|
|
|
|
|
2010-09-01 05:24:31 +00:00
|
|
|
ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error allocating channel PRAMIN: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-09-01 05:24:30 +00:00
|
|
|
ret = drm_mm_init(&chan->ramin_heap, base, size);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error creating PRAMIN heap: %d\n", ret);
|
2010-09-01 05:24:31 +00:00
|
|
|
nouveau_gpuobj_ref(NULL, &chan->ramin);
|
2009-12-11 09:24:15 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
|
|
|
|
uint32_t vram_h, uint32_t tt_h)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = chan->dev;
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
|
|
|
|
struct nouveau_gpuobj *vram = NULL, *tt = NULL;
|
|
|
|
int ret, i;
|
|
|
|
|
|
|
|
NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
|
|
|
|
|
2010-07-08 03:15:05 +00:00
|
|
|
/* Allocate a chunk of memory for per-channel object storage */
|
|
|
|
ret = nouveau_gpuobj_channel_init_pramin(chan);
|
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "init pramin\n");
|
|
|
|
return ret;
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* NV50 VM
|
|
|
|
* - Allocate per-channel page-directory
|
|
|
|
* - Map GART and VRAM into the channel's address space at the
|
|
|
|
* locations determined during init.
|
|
|
|
*/
|
|
|
|
if (dev_priv->card_type >= NV_50) {
|
2010-09-01 05:24:33 +00:00
|
|
|
u32 pgd_offs = (dev_priv->chipset == 0x50) ? 0x1400 : 0x0200;
|
|
|
|
u64 vm_vinst = chan->ramin->vinst + pgd_offs;
|
|
|
|
u32 vm_pinst = chan->ramin->pinst;
|
|
|
|
u32 pde;
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-09-01 05:24:33 +00:00
|
|
|
if (vm_pinst != ~0)
|
|
|
|
vm_pinst += pgd_offs;
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-09-01 05:24:33 +00:00
|
|
|
ret = nouveau_gpuobj_new_fake(dev, vm_pinst, vm_vinst, 0x4000,
|
2010-09-01 05:24:31 +00:00
|
|
|
0, &chan->vm_pd);
|
2010-07-08 01:29:10 +00:00
|
|
|
if (ret)
|
2009-12-11 09:24:15 +00:00
|
|
|
return ret;
|
|
|
|
for (i = 0; i < 0x4000; i += 8) {
|
2010-09-01 05:24:29 +00:00
|
|
|
nv_wo32(chan->vm_pd, i + 0, 0x00000000);
|
|
|
|
nv_wo32(chan->vm_pd, i + 4, 0xdeadcafe);
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
2010-09-01 05:24:31 +00:00
|
|
|
nouveau_gpuobj_ref(dev_priv->gart_info.sg_ctxdma,
|
|
|
|
&chan->vm_gart_pt);
|
2010-09-01 05:24:29 +00:00
|
|
|
pde = (dev_priv->vm_gart_base / (512*1024*1024)) * 8;
|
2010-09-01 05:24:31 +00:00
|
|
|
nv_wo32(chan->vm_pd, pde + 0, chan->vm_gart_pt->vinst | 3);
|
2010-09-01 05:24:29 +00:00
|
|
|
nv_wo32(chan->vm_pd, pde + 4, 0x00000000);
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-09-01 05:24:29 +00:00
|
|
|
pde = (dev_priv->vm_vram_base / (512*1024*1024)) * 8;
|
2009-12-11 09:24:15 +00:00
|
|
|
for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {
|
2010-09-01 05:24:31 +00:00
|
|
|
nouveau_gpuobj_ref(dev_priv->vm_vram_pt[i],
|
|
|
|
&chan->vm_vram_pt[i]);
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-09-01 05:24:29 +00:00
|
|
|
nv_wo32(chan->vm_pd, pde + 0,
|
2010-09-01 05:24:31 +00:00
|
|
|
chan->vm_vram_pt[i]->vinst | 0x61);
|
2010-09-01 05:24:29 +00:00
|
|
|
nv_wo32(chan->vm_pd, pde + 4, 0x00000000);
|
|
|
|
pde += 8;
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
2010-07-08 01:29:10 +00:00
|
|
|
instmem->flush(dev);
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* RAMHT */
|
|
|
|
if (dev_priv->card_type < NV_50) {
|
2010-09-01 05:24:31 +00:00
|
|
|
nouveau_ramht_ref(dev_priv->ramht, &chan->ramht, NULL);
|
|
|
|
} else {
|
|
|
|
struct nouveau_gpuobj *ramht = NULL;
|
|
|
|
|
|
|
|
ret = nouveau_gpuobj_new(dev, chan, 0x8000, 16,
|
|
|
|
NVOBJ_FLAG_ZERO_ALLOC, &ramht);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2010-09-01 05:24:31 +00:00
|
|
|
|
|
|
|
ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
|
|
|
|
nouveau_gpuobj_ref(NULL, &ramht);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* VRAM ctxdma */
|
|
|
|
if (dev_priv->card_type >= NV_50) {
|
|
|
|
ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
|
|
|
|
0, dev_priv->vm_end,
|
|
|
|
NV_DMA_ACCESS_RW,
|
|
|
|
NV_DMA_TARGET_AGP, &vram);
|
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
|
2010-09-01 05:24:31 +00:00
|
|
|
0, dev_priv->fb_available_size,
|
|
|
|
NV_DMA_ACCESS_RW,
|
|
|
|
NV_DMA_TARGET_VIDMEM, &vram);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-09-01 05:24:31 +00:00
|
|
|
ret = nouveau_ramht_insert(chan, vram_h, vram);
|
|
|
|
nouveau_gpuobj_ref(NULL, &vram);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret) {
|
2010-09-01 05:24:31 +00:00
|
|
|
NV_ERROR(dev, "Error adding VRAM ctxdma to RAMHT: %d\n", ret);
|
2009-12-11 09:24:15 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* TT memory ctxdma */
|
|
|
|
if (dev_priv->card_type >= NV_50) {
|
2010-09-01 05:24:31 +00:00
|
|
|
ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
|
|
|
|
0, dev_priv->vm_end,
|
|
|
|
NV_DMA_ACCESS_RW,
|
|
|
|
NV_DMA_TARGET_AGP, &tt);
|
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
2009-12-11 09:24:15 +00:00
|
|
|
} else
|
|
|
|
if (dev_priv->gart_info.type != NOUVEAU_GART_NONE) {
|
|
|
|
ret = nouveau_gpuobj_gart_dma_new(chan, 0,
|
|
|
|
dev_priv->gart_info.aper_size,
|
|
|
|
NV_DMA_ACCESS_RW, &tt, NULL);
|
|
|
|
} else {
|
|
|
|
NV_ERROR(dev, "Invalid GART type %d\n", dev_priv->gart_info.type);
|
|
|
|
ret = -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error creating TT ctxdma: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-09-01 05:24:31 +00:00
|
|
|
ret = nouveau_ramht_insert(chan, tt_h, tt);
|
|
|
|
nouveau_gpuobj_ref(NULL, &tt);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret) {
|
2010-09-01 05:24:31 +00:00
|
|
|
NV_ERROR(dev, "Error adding TT ctxdma to RAMHT: %d\n", ret);
|
2009-12-11 09:24:15 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan)
|
|
|
|
{
|
|
|
|
struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
|
|
|
|
struct drm_device *dev = chan->dev;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
NV_DEBUG(dev, "ch%d\n", chan->id);
|
|
|
|
|
2010-09-01 05:24:31 +00:00
|
|
|
if (!chan->ramht)
|
2009-12-11 09:24:15 +00:00
|
|
|
return;
|
|
|
|
|
2010-09-01 05:24:31 +00:00
|
|
|
nouveau_ramht_ref(NULL, &chan->ramht, chan);
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-09-01 05:24:31 +00:00
|
|
|
nouveau_gpuobj_ref(NULL, &chan->vm_pd);
|
|
|
|
nouveau_gpuobj_ref(NULL, &chan->vm_gart_pt);
|
2009-12-11 09:24:15 +00:00
|
|
|
for (i = 0; i < dev_priv->vm_vram_pt_nr; i++)
|
2010-09-01 05:24:31 +00:00
|
|
|
nouveau_gpuobj_ref(NULL, &chan->vm_vram_pt[i]);
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-06-01 05:32:24 +00:00
|
|
|
if (chan->ramin_heap.free_stack.next)
|
|
|
|
drm_mm_takedown(&chan->ramin_heap);
|
2010-09-01 05:24:31 +00:00
|
|
|
nouveau_gpuobj_ref(NULL, &chan->ramin);
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
nouveau_gpuobj_suspend(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
struct nouveau_gpuobj *gpuobj;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (dev_priv->card_type < NV_50) {
|
|
|
|
dev_priv->susres.ramin_copy = vmalloc(dev_priv->ramin_rsvd_vram);
|
|
|
|
if (!dev_priv->susres.ramin_copy)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4)
|
|
|
|
dev_priv->susres.ramin_copy[i/4] = nv_ri32(dev, i);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
|
2010-09-01 05:24:32 +00:00
|
|
|
if (!gpuobj->im_backing)
|
2009-12-11 09:24:15 +00:00
|
|
|
continue;
|
|
|
|
|
2010-09-01 05:24:32 +00:00
|
|
|
gpuobj->im_backing_suspend = vmalloc(gpuobj->size);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (!gpuobj->im_backing_suspend) {
|
|
|
|
nouveau_gpuobj_resume(dev);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2010-09-01 05:24:32 +00:00
|
|
|
for (i = 0; i < gpuobj->size; i += 4)
|
2010-09-01 05:24:29 +00:00
|
|
|
gpuobj->im_backing_suspend[i/4] = nv_ro32(gpuobj, i);
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
nouveau_gpuobj_suspend_cleanup(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
struct nouveau_gpuobj *gpuobj;
|
|
|
|
|
|
|
|
if (dev_priv->card_type < NV_50) {
|
|
|
|
vfree(dev_priv->susres.ramin_copy);
|
|
|
|
dev_priv->susres.ramin_copy = NULL;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
|
|
|
|
if (!gpuobj->im_backing_suspend)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
vfree(gpuobj->im_backing_suspend);
|
|
|
|
gpuobj->im_backing_suspend = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
nouveau_gpuobj_resume(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
struct nouveau_gpuobj *gpuobj;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (dev_priv->card_type < NV_50) {
|
|
|
|
for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4)
|
|
|
|
nv_wi32(dev, i, dev_priv->susres.ramin_copy[i/4]);
|
|
|
|
nouveau_gpuobj_suspend_cleanup(dev);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
|
|
|
|
if (!gpuobj->im_backing_suspend)
|
|
|
|
continue;
|
|
|
|
|
2010-09-01 05:24:32 +00:00
|
|
|
for (i = 0; i < gpuobj->size; i += 4)
|
2010-09-01 05:24:29 +00:00
|
|
|
nv_wo32(gpuobj, i, gpuobj->im_backing_suspend[i/4]);
|
2010-07-08 01:29:10 +00:00
|
|
|
dev_priv->engine.instmem.flush(dev);
|
2009-12-11 09:24:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
nouveau_gpuobj_suspend_cleanup(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv)
|
|
|
|
{
|
|
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_nouveau_grobj_alloc *init = data;
|
|
|
|
struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
|
|
|
|
struct nouveau_pgraph_object_class *grc;
|
|
|
|
struct nouveau_gpuobj *gr = NULL;
|
|
|
|
struct nouveau_channel *chan;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(init->channel, file_priv, chan);
|
|
|
|
|
|
|
|
if (init->handle == ~0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
grc = pgraph->grclass;
|
|
|
|
while (grc->id) {
|
|
|
|
if (grc->id == init->class)
|
|
|
|
break;
|
|
|
|
grc++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!grc->id) {
|
|
|
|
NV_ERROR(dev, "Illegal object class: 0x%x\n", init->class);
|
|
|
|
return -EPERM;
|
|
|
|
}
|
|
|
|
|
2010-09-01 05:24:31 +00:00
|
|
|
if (nouveau_ramht_find(chan, init->handle))
|
2009-12-11 09:24:15 +00:00
|
|
|
return -EEXIST;
|
|
|
|
|
|
|
|
if (!grc->software)
|
|
|
|
ret = nouveau_gpuobj_gr_new(chan, grc->id, &gr);
|
|
|
|
else
|
|
|
|
ret = nouveau_gpuobj_sw_new(chan, grc->id, &gr);
|
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n",
|
|
|
|
ret, init->channel, init->handle);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-09-01 05:24:31 +00:00
|
|
|
ret = nouveau_ramht_insert(chan, init->handle, gr);
|
|
|
|
nouveau_gpuobj_ref(NULL, &gr);
|
2009-12-11 09:24:15 +00:00
|
|
|
if (ret) {
|
|
|
|
NV_ERROR(dev, "Error referencing object: %d (%d/0x%08x)\n",
|
|
|
|
ret, init->channel, init->handle);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv)
|
|
|
|
{
|
|
|
|
struct drm_nouveau_gpuobj_free *objfree = data;
|
2010-09-01 05:24:31 +00:00
|
|
|
struct nouveau_gpuobj *gpuobj;
|
2009-12-11 09:24:15 +00:00
|
|
|
struct nouveau_channel *chan;
|
|
|
|
|
|
|
|
NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(objfree->channel, file_priv, chan);
|
|
|
|
|
2010-09-01 05:24:31 +00:00
|
|
|
gpuobj = nouveau_ramht_find(chan, objfree->handle);
|
|
|
|
if (!gpuobj)
|
|
|
|
return -ENOENT;
|
2009-12-11 09:24:15 +00:00
|
|
|
|
2010-09-01 05:24:31 +00:00
|
|
|
nouveau_ramht_remove(chan, objfree->handle);
|
2009-12-11 09:24:15 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2010-09-01 05:24:29 +00:00
|
|
|
|
|
|
|
u32
|
|
|
|
nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset)
|
|
|
|
{
|
2010-09-01 05:24:33 +00:00
|
|
|
struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
|
|
|
|
struct drm_device *dev = gpuobj->dev;
|
|
|
|
|
|
|
|
if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
|
|
|
|
u64 ptr = gpuobj->vinst + offset;
|
|
|
|
u32 base = ptr >> 16;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
spin_lock(&dev_priv->ramin_lock);
|
|
|
|
if (dev_priv->ramin_base != base) {
|
|
|
|
dev_priv->ramin_base = base;
|
|
|
|
nv_wr32(dev, 0x001700, dev_priv->ramin_base);
|
|
|
|
}
|
|
|
|
val = nv_rd32(dev, 0x700000 + (ptr & 0xffff));
|
|
|
|
spin_unlock(&dev_priv->ramin_lock);
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
return nv_ri32(dev, gpuobj->pinst + offset);
|
2010-09-01 05:24:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
nv_wo32(struct nouveau_gpuobj *gpuobj, u32 offset, u32 val)
|
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{
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2010-09-01 05:24:33 +00:00
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struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
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struct drm_device *dev = gpuobj->dev;
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if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
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u64 ptr = gpuobj->vinst + offset;
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u32 base = ptr >> 16;
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spin_lock(&dev_priv->ramin_lock);
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if (dev_priv->ramin_base != base) {
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dev_priv->ramin_base = base;
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nv_wr32(dev, 0x001700, dev_priv->ramin_base);
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}
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nv_wr32(dev, 0x700000 + (ptr & 0xffff), val);
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spin_unlock(&dev_priv->ramin_lock);
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return;
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}
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nv_wi32(dev, gpuobj->pinst + offset, val);
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2010-09-01 05:24:29 +00:00
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}
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