211 lines
7.7 KiB
Verilog
211 lines
7.7 KiB
Verilog
`timescale 1ns / 1ps
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module top(
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input clk50m,
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input uart_rx_pin,
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output uart_tx_pin,
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input reset_n,
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output IO_A5,
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output sdram_clk ,//connected to the CLK port of SDRAM
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output sdram_cke ,//connected to the CKE port of SDRAM
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output sdram_cs_n ,//connected to the CS_n port of SDRAM
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output sdram_ras_n ,//connected to the RAS_n port of SDRAM
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output sdram_cas_n ,//connected to the CAS_n port of SDRAM
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output sdram_we_n ,//connected to the WE_n port of SDRAM
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/*output sdram_ba ,//connected to the BA port of SDRAM
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output sdram_addr ,//connected to the ADDR port of SDRAM
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output sdram_dqm ,//connected to the DQM port of SDRAM
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inout sdram_dq //connected to the DQ port of SDRAM*/
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///
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output [BANK_WIDTH-1 : 0] sdram_ba,
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output [ROW_WIDTH-1 : 0] sdram_addr,
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output [DQ_WIDTH/8-1: 0] sdram_dqm,
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inout [DQ_WIDTH-1 : 0] sdram_dq
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);
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parameter COL_WIDTH = 9;//2^9 = 512 addresses in each colum
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parameter ROW_WIDTH = 13;//2^13 = 8192 addresses in each bank
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parameter BANK_WIDTH = 2;//2^2 = 4 banks in a single chip
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parameter DQ_WIDTH = 16;//16 bit Data Bus for one chip
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parameter [12:0] SDRAM_MR = 13'h0037;//Full Page Burst,Latency=3,Burst Read and Burst Write,Standard mode
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//parameter DDR_PRIMITIVE_TYPE = "VIRTEX5" ;//FPGA is Virtex-5 serirals
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parameter DDR_PRIMITIVE_TYPE = "SPARTEN6";//FPGA is Sparten-6 serirals
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wire reset = ~reset_n;
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wire clk125, clk125_ram;
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//wire cbuf = clk50m;
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clock_pll pll(.clkin(clk50m),
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.clk125(clk125),
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.clk125_ram(clk125_ram),
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.reset(reset)
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);
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wire clk = clk125;
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parameter ClkFrequency = 125000000;
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parameter Baud = 115200;
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parameter BaudGeneratorAccWidth = 24;
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//parameter BaudGeneratorInc = (Baud<<BaudGeneratorAccWidth)/ClkFrequency;
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initial begin
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$display ("%d", 10);
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end
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parameter BaudGeneratorInc = 15462;
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//parameter BaudGeneratorInc = 966;
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reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
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always @(posedge clk)
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BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;
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wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
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wire transmit_avail;
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wire receive_avail;
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reg rx_present_clear;
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wire [7:0] rec_byte;
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reg [7:0] tx_byte;
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reg tx_latch;
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uart_controller uart(
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.tx_data_in(tx_byte),
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.tx_data_latch(tx_latch),
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.clock(BaudTick),
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.reset(reset),
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.tx_transmitted(transmit_avail),
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.tx_signal(uart_tx_pin),
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.rx_present(receive_avail),
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.rx_present_clear(rx_present_clear),
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.rx_data(rec_byte),
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.rx_signal(uart_rx_pin)
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);
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reg [3:0] state;
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`define IDLE 0
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`define SENDING 1
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`define TX_WAIT 2
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assign IO_A5 = BaudGeneratorAcc[BaudGeneratorAccWidth-1];
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wire [8:0] user_burst_length;
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assign user_burst_length = 9'h1FF;
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wire user_command_gnt;
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reg user_command_req;
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wire user_rd0_wr1 = 0;
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reg [BANK_WIDTH+ROW_WIDTH+COL_WIDTH-1 : 0] user_start_addr;
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wire sdram_data_valid;
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wire [DQ_WIDTH-1 :0] sdram_rd_data;
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reg has_byte;
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wire Tx_fifo_rd_en;
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reg [DQ_WIDTH/8+DQ_WIDTH-1 :0 ] txreg;
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reg Tx_fifo_wr_en;
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wire [DQ_WIDTH/8+DQ_WIDTH-1 : 0] Tx_fifo_rd_data;
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wire Tx_fifo_almost_full;
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wire Tx_fifo_almost_empty;
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always @(posedge clk) begin
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if (reset) begin
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tx_byte <= "A";
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tx_latch <= 0;
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rx_present_clear <= 0;
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state <= `IDLE;
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has_byte <= 0;
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end
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if (!tx_latch && receive_avail) begin
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tx_byte <= rec_byte;
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has_byte <= 1;
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rx_present_clear <= 1;
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end
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if (rx_present_clear && !receive_avail)
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rx_present_clear <= 0;
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case (state)
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`IDLE: begin
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if (has_byte && BaudTick) begin
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tx_latch <= 1;
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state <= `TX_WAIT;
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end
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end
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`TX_WAIT: begin
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if(!transmit_avail) begin
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tx_latch <= 0;
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has_byte <= 0;
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state <= `SENDING;
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end
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end
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`SENDING: begin
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if(transmit_avail) begin
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state <= `IDLE;
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end
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//state = `TX_WAIT;
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end
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endcase
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///////////////
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txreg <= txreg + 1;
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if(Tx_fifo_wr_en)
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Tx_fifo_wr_en <= 0;
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if(!Tx_fifo_almost_full)
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Tx_fifo_wr_en <= 1;
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else
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user_command_req <= 1;
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if(user_command_req)
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user_command_req <= 0;
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if(user_command_gnt)
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user_start_addr <= user_start_addr + 1;
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if(sdram_data_valid)
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tx_byte <= sdram_rd_data;
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end
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sdram_driver_v2 #
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(
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.COL_WIDTH (COL_WIDTH ),
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.ROW_WIDTH (ROW_WIDTH ),
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.BANK_WIDTH (BANK_WIDTH ),
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.DQ_WIDTH (DQ_WIDTH ),
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.SDRAM_MR (SDRAM_MR ),
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.DDR_PRIMITIVE_TYPE(DDR_PRIMITIVE_TYPE)
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)
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u_sdram_driver_v2(
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.clk0(clk125),//The main clock of the control system
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.clk1(clk125_ram),//have the same period of clk, but the phase is shifted
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.rst_n(reset_n),
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.user_command_req(user_command_req ),//The user want to send a read/write command,active HIGH
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.user_command_gnt (user_command_gnt ),//The state machine have accept the user's read/write command
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.user_rd0_wr1 (user_rd0_wr1 ),//HIGH voltage means read and a low means write,synchronous to "user_command_req"
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.user_burst_length(user_burst_length),//Express the read/write lenghth of each command,synchronous to "user_command_req"
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.user_start_addr (user_start_addr ),//the user's read/write address,synchronous to "user_command_req"
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.Tx_fifo_rd_en (Tx_fifo_rd_en ),//used in the user's write command,this port is synchronous to "clk"
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.Tx_fifo_rd_data (Tx_fifo_rd_data ),//the user write data to the fifo,synchronous to "clk"
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.sdram_data_valid(sdram_data_valid),//tell the user that valid read data is coming,active HIGH
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.sdram_rd_data (sdram_rd_data ),//synchronous to sdram_data_valid
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.sdram_clk (sdram_clk ),//connected to the CLK port of SDRAM
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.sdram_cke (sdram_cke ),//connected to the CKE port of SDRAM
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.sdram_cs_n (sdram_cs_n ),//connected to the CS_n port of SDRAM
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.sdram_ras_n (sdram_ras_n),//connected to the RAS_n port of SDRAM
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.sdram_cas_n (sdram_cas_n),//connected to the CAS_n port of SDRAM
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.sdram_we_n (sdram_we_n ),//connected to the WE_n port of SDRAM
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.sdram_ba (sdram_ba ),//connected to the BA port of SDRAM
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.sdram_addr (sdram_addr ),//connected to the ADDR port of SDRAM
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.sdram_dqm (sdram_dqm ),//connected to the DQM port of SDRAM
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.sdram_dq (sdram_dq ) //connected to the DQ port of SDRAM
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);
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Tx_fifo U_Tx_fifo(
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.clk (clk ), // input clk
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.srst (reset ), // input srst
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.din (txreg ), // input [35 : 0] din
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.wr_en (Tx_fifo_wr_en ), // input wr_en
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.rd_en (Tx_fifo_rd_en ), // input rd_en
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.dout (Tx_fifo_rd_data ), // output [35 : 0] dout
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.full ( ), // output full
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.empty ( ), // output empty
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.prog_full (Tx_fifo_almost_full ), // output prog_full
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.prog_empty(Tx_fifo_almost_empty) // output prog_empty
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);
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endmodule
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