ledmatrix/top.v

`timescale 1ns / 1ps
module top(
    input clk50m,
    input uart_rx_pin,
    output uart_tx_pin,
    input reset_n,
    output IO_A5,

    output sdram_clk      ,//connected to the CLK port of SDRAM  
    output sdram_cke      ,//connected to the CKE port of SDRAM  
    output sdram_cs_n     ,//connected to the CS_n port of SDRAM 
    output sdram_ras_n    ,//connected to the RAS_n port of SDRAM
    output sdram_cas_n    ,//connected to the CAS_n port of SDRAM
    output sdram_we_n     ,//connected to the WE_n port of SDRAM 
    /*output sdram_ba       ,//connected to the BA port of SDRAM 
    output sdram_addr     ,//connected to the ADDR port of SDRAM   
    output sdram_dqm      ,//connected to the DQM port of SDRAM 
    inout sdram_dq        //connected to the DQ port of SDRAM*/
    ///
    output [BANK_WIDTH-1 : 0]     sdram_ba,
    output [ROW_WIDTH-1 : 0]      sdram_addr,
    output [DQ_WIDTH/8-1: 0]      sdram_dqm,
    inout  [DQ_WIDTH-1 : 0]       sdram_dq

    );

    parameter COL_WIDTH          = 9;//2^9 = 512 addresses in each colum
    parameter ROW_WIDTH          = 13;//2^13 = 8192 addresses in each bank
    parameter BANK_WIDTH         = 2;//2^2 = 4 banks in a single chip
    parameter DQ_WIDTH           = 16;//16 bit Data Bus for one chip
    parameter [12:0]      SDRAM_MR           = 13'h0037;//Full Page Burst,Latency=3,Burst Read and Burst Write,Standard mode
    //parameter           DDR_PRIMITIVE_TYPE = "VIRTEX5" ;//FPGA is Virtex-5 serirals
    parameter DDR_PRIMITIVE_TYPE = "SPARTEN6";//FPGA is Sparten-6 serirals

    wire reset = ~reset_n;

    wire clk125, clk125_ram;
    //wire cbuf = clk50m;
    clock_pll pll(.clkin(clk50m),
        .clk125(clk125),
        .clk125_ram(clk125_ram),
        .reset(reset)
    );
    wire clk = clk125;

    parameter ClkFrequency = 125000000;
    parameter Baud = 115200;
    parameter BaudGeneratorAccWidth = 24;
    //parameter  BaudGeneratorInc = (Baud<<BaudGeneratorAccWidth)/ClkFrequency;
    initial begin
        $display ("%d", 10);
    end
    parameter BaudGeneratorInc = 15462;
    //parameter BaudGeneratorInc = 966;

    reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
    always @(posedge clk)
        BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;

    wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];

    wire transmit_avail;
    wire receive_avail;
    reg rx_present_clear;
    wire [7:0] rec_byte;
    reg [7:0] tx_byte;
    reg tx_latch;

    uart_controller uart(
        .tx_data_in(tx_byte),
        .tx_data_latch(tx_latch),
        .clock(BaudTick),
        .reset(reset),
        .tx_transmitted(transmit_avail),
        .tx_signal(uart_tx_pin),
        .rx_present(receive_avail),
        .rx_present_clear(rx_present_clear),
        .rx_data(rec_byte),
        .rx_signal(uart_rx_pin)	
    );

    reg [3:0] state;
    `define IDLE 0
    `define SENDING 1
    `define TX_WAIT 2

    assign IO_A5 = BaudGeneratorAcc[BaudGeneratorAccWidth-1];

    wire [8:0] user_burst_length;
    assign user_burst_length = 9'h1FF;
    wire user_command_gnt;
    reg user_command_req;
    wire user_rd0_wr1 = 0;
    reg [BANK_WIDTH+ROW_WIDTH+COL_WIDTH-1 : 0] user_start_addr;
    wire sdram_data_valid;
    wire [DQ_WIDTH-1 :0] sdram_rd_data;

    reg has_byte;
    
    wire Tx_fifo_rd_en;  
    reg [DQ_WIDTH/8+DQ_WIDTH-1 :0 ] txreg;	
    reg Tx_fifo_wr_en;
    wire [DQ_WIDTH/8+DQ_WIDTH-1 : 0] Tx_fifo_rd_data;
    wire Tx_fifo_almost_full;
    wire Tx_fifo_almost_empty;

    always @(posedge clk) begin
        if (reset) begin
            tx_byte <= "A";
            tx_latch <= 0;
            rx_present_clear <= 0;
            state <= `IDLE;
            has_byte <= 0;
        end
        if (!tx_latch && receive_avail) begin
            tx_byte <= rec_byte;
            has_byte <= 1;
            rx_present_clear <= 1;
        end
        if (rx_present_clear && !receive_avail)
            rx_present_clear <= 0;
        case (state)
            `IDLE: begin
                if (has_byte && BaudTick) begin
                    tx_latch <= 1;
                    state <= `TX_WAIT;
                end
            end
            `TX_WAIT: begin
                if(!transmit_avail) begin
                    tx_latch <= 0;
                    has_byte <= 0;
                    state <= `SENDING;
                end
            end
            `SENDING: begin
                if(transmit_avail) begin
                    state <= `IDLE;
                end
                //state = `TX_WAIT;
            end
        endcase


        ///////////////
        txreg <= txreg + 1;
        if(Tx_fifo_wr_en)
            Tx_fifo_wr_en <= 0;
        if(!Tx_fifo_almost_full)
            Tx_fifo_wr_en <= 1;
        else
            user_command_req <= 1;
        if(user_command_req)
            user_command_req <= 0;

        if(user_command_gnt)
            user_start_addr <= user_start_addr + 1;
        if(sdram_data_valid)
            tx_byte <= sdram_rd_data;
    end

    sdram_driver_v2 #
    (
        .COL_WIDTH         (COL_WIDTH         ),
        .ROW_WIDTH         (ROW_WIDTH         ),
        .BANK_WIDTH        (BANK_WIDTH        ),
        .DQ_WIDTH          (DQ_WIDTH          ),
        .SDRAM_MR          (SDRAM_MR          ),
        .DDR_PRIMITIVE_TYPE(DDR_PRIMITIVE_TYPE)
    )
    u_sdram_driver_v2(
        .clk0(clk125),//The main clock of the control system
        .clk1(clk125_ram),//have the same period of clk, but the phase is shifted
        .rst_n(reset_n),
        .user_command_req(user_command_req ),//The user want to send a read/write command,active HIGH
        .user_command_gnt (user_command_gnt ),//The state machine have accept the user's read/write command
        .user_rd0_wr1     (user_rd0_wr1     ),//HIGH voltage means read and a low means write,synchronous to "user_command_req"
        .user_burst_length(user_burst_length),//Express the read/write lenghth of each command,synchronous to "user_command_req"
        .user_start_addr  (user_start_addr  ),//the user's read/write address,synchronous to "user_command_req"
        .Tx_fifo_rd_en    (Tx_fifo_rd_en    ),//used in the user's write command,this port is synchronous to "clk"
        .Tx_fifo_rd_data  (Tx_fifo_rd_data  ),//the user write data to the fifo,synchronous to "clk"

        .sdram_data_valid(sdram_data_valid),//tell the user that valid read data is coming,active HIGH
        .sdram_rd_data   (sdram_rd_data   ),//synchronous to sdram_data_valid

        .sdram_clk   (sdram_clk  ),//connected to the CLK port of SDRAM  
        .sdram_cke   (sdram_cke  ),//connected to the CKE port of SDRAM  
        .sdram_cs_n  (sdram_cs_n ),//connected to the CS_n port of SDRAM 
        .sdram_ras_n (sdram_ras_n),//connected to the RAS_n port of SDRAM
        .sdram_cas_n (sdram_cas_n),//connected to the CAS_n port of SDRAM
        .sdram_we_n  (sdram_we_n ),//connected to the WE_n port of SDRAM 
        .sdram_ba    (sdram_ba   ),//connected to the BA port of SDRAM 
        .sdram_addr  (sdram_addr ),//connected to the ADDR port of SDRAM   
        .sdram_dqm   (sdram_dqm  ),//connected to the DQM port of SDRAM 
        .sdram_dq    (sdram_dq   ) //connected to the DQ port of SDRAM
    );

    Tx_fifo U_Tx_fifo(
        .clk       (clk                ), // input clk
        .srst      (reset              ), // input srst
        .din       (txreg     ), // input [35 : 0] din
        .wr_en     (Tx_fifo_wr_en       ), // input wr_en
        .rd_en     (Tx_fifo_rd_en       ), // input rd_en
        .dout      (Tx_fifo_rd_data     ), // output [35 : 0] dout
        .full      (                    ), // output full
        .empty     (                    ), // output empty
        .prog_full (Tx_fifo_almost_full ), // output prog_full
        .prog_empty(Tx_fifo_almost_empty)  // output prog_empty
    );

endmodule