134 lines
4.5 KiB
Verilog
134 lines
4.5 KiB
Verilog
// Taken from github.com/B-Lang-org/bsc, file src/Verilog/BRAM2Load.v.
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// Modified to remove write enable from second port, allowing Yosys to infer
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// that this is not a true dual-ported BRAM.
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//
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// Copyright (c) 2020 Bluespec, Inc. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// SPDX-License-Identifier: BSD-3-Clause
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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// Dual-Ported BRAM (WRITE FIRST)
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module BRAM2Load(CLKA,
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ENA,
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WEA,
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ADDRA,
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DIA,
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DOA,
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CLKB,
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ENB,
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WEB,
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ADDRB,
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DIB,
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DOB
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);
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parameter FILENAME = "";
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parameter PIPELINED = 0;
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parameter ADDR_WIDTH = 1;
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parameter DATA_WIDTH = 1;
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parameter MEMSIZE = 1;
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parameter BINARY = 0;
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input CLKA;
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input ENA;
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input WEA;
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input [ADDR_WIDTH-1:0] ADDRA;
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input [DATA_WIDTH-1:0] DIA;
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output [DATA_WIDTH-1:0] DOA;
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input CLKB;
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input ENB;
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input WEB;
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input [ADDR_WIDTH-1:0] ADDRB;
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input [DATA_WIDTH-1:0] DIB;
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output [DATA_WIDTH-1:0] DOB;
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reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
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reg [DATA_WIDTH-1:0] DOA_R;
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reg [DATA_WIDTH-1:0] DOB_R;
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reg [DATA_WIDTH-1:0] DOA_R2;
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reg [DATA_WIDTH-1:0] DOB_R2;
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// synopsys translate_off
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initial
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begin : init_block
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`ifdef BSV_NO_INITIAL_BLOCKS
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`else
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DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
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DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
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DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
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DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
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`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
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end
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// synopsys translate_on
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initial
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begin : init_rom_block
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if (BINARY)
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$readmemb(FILENAME, RAM, 0, MEMSIZE-1);
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else
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$readmemh(FILENAME, RAM, 0, MEMSIZE-1);
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end
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always @(posedge CLKA) begin
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if (ENA) begin
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//if (WEA) begin
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// RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
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// DOA_R <= `BSV_ASSIGNMENT_DELAY DIA;
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//end else begin
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DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
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//end
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end
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DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
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end
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always @(posedge CLKB) begin
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if (ENB) begin
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if (WEB) begin
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RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
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DOB_R <= `BSV_ASSIGNMENT_DELAY DIB;
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end
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else begin
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DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
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end
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end
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DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
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end
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// Output drivers
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assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
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assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
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endmodule // BRAM2Load
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