build: initial pass at bluespec/yosys/nextpnr infra
commit
f0d305410e
|
@ -0,0 +1,2 @@
|
|||
bazel-*
|
||||
**swp
|
|
@ -0,0 +1,287 @@
|
|||
EUROPEAN UNION PUBLIC LICENCE v. 1.2
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EUPL © the European Union 2007, 2016
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The Work is a work in progress, which is continuously improved by numerous
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Appendix
|
||||
|
||||
‘Compatible Licences’ according to Article 5 EUPL are:
|
||||
|
||||
- GNU General Public License (GPL) v. 2, v. 3
|
||||
- GNU Affero General Public License (AGPL) v. 3
|
||||
- Open Software License (OSL) v. 2.1, v. 3.0
|
||||
- Eclipse Public License (EPL) v. 1.0
|
||||
- CeCILL v. 2.0, v. 2.1
|
||||
- Mozilla Public Licence (MPL) v. 2
|
||||
- GNU Lesser General Public Licence (LGPL) v. 2.1, v. 3
|
||||
- Creative Commons Attribution-ShareAlike v. 3.0 Unported (CC BY-SA 3.0) for
|
||||
works other than software
|
||||
- European Union Public Licence (EUPL) v. 1.1, v. 1.2
|
||||
- Québec Free and Open-Source Licence — Reciprocity (LiLiQ-R) or Strong
|
||||
Reciprocity (LiLiQ-R+).
|
||||
|
||||
The European Commission may update this Appendix to later versions of the above
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licences without producing a new version of the EUPL, as long as they provide
|
||||
the rights granted in Article 2 of this Licence and protect the covered Source
|
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Code from exclusive appropriation.
|
||||
|
||||
All other changes or additions to this Appendix require the production of a new
|
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EUPL version.
|
|
@ -0,0 +1,9 @@
|
|||
qfc
|
||||
===
|
||||
|
||||
q3k's {fpga,fantasy,fancy,futile,funky} computer
|
||||
|
||||
License
|
||||
-------
|
||||
|
||||
Unless otherwise specified, all files within this repository are licensed under the EUPL v. 1.2 only. See COPYING for more information.
|
|
@ -0,0 +1,122 @@
|
|||
workspace(
|
||||
name = "qfc",
|
||||
)
|
||||
|
||||
load("@bazel_tools//tools/build_defs/repo:http.bzl", "http_archive")
|
||||
|
||||
http_archive(
|
||||
name = "io_tweag_rules_nixpkgs",
|
||||
strip_prefix = "rules_nixpkgs-a388ab60dea07c3fc182453e89ff1a67c9d3eba6",
|
||||
urls = ["https://github.com/tweag/rules_nixpkgs/archive/a388ab60dea07c3fc182453e89ff1a67c9d3eba6.tar.gz"],
|
||||
sha256 = "6bedf80d6cb82d3f1876e27f2ff9a2cc814d65f924deba14b49698bb1fb2a7f7",
|
||||
)
|
||||
|
||||
load("@io_tweag_rules_nixpkgs//nixpkgs:repositories.bzl", "rules_nixpkgs_dependencies")
|
||||
rules_nixpkgs_dependencies()
|
||||
|
||||
load("@io_tweag_rules_nixpkgs//nixpkgs:nixpkgs.bzl", "nixpkgs_git_repository", "nixpkgs_package")
|
||||
|
||||
nixpkgs_git_repository(
|
||||
name = "nixpkgs",
|
||||
revision = "7b2982e22eb3ca5016161abc0946f88bb43b1e09",
|
||||
sha256 = "c1b0483e6f34fe8f011ef424e0d59196c0f66a0e7a0a89d2e4b12986b43794ca",
|
||||
)
|
||||
|
||||
nixpkgs_package(
|
||||
name = "bluespec",
|
||||
repositories = { "nixpkgs": "@nixpkgs//:default.nix" },
|
||||
build_file_content = """
|
||||
load("@qfc//build:utils.bzl", "external_binary_tool")
|
||||
load("@qfc//build/bluespec:rules.bzl", "bluespec_toolchain")
|
||||
|
||||
external_binary_tool(
|
||||
name = "bsc",
|
||||
bin = "bin/bsc",
|
||||
deps = glob(["lib/**", "bin/core/**"]),
|
||||
)
|
||||
|
||||
bluespec_toolchain(
|
||||
name = "bsc_nixpkgs",
|
||||
bsc = ":bsc",
|
||||
verilog_lib = glob(["lib/Verilog/*.v"], [
|
||||
"lib/Verilog/BRAM*Load.v",
|
||||
"lib/Verilog/ConstrainedRandom.v",
|
||||
"lib/Verilog/Convert*Z.v",
|
||||
"lib/Verilog/InoutConnect.v",
|
||||
"lib/Verilog/ProbeHook.v",
|
||||
"lib/Verilog/RegFileLoad.v",
|
||||
"lib/Verilog/ResolveZ.v",
|
||||
"lib/Verilog/main.v",
|
||||
]),
|
||||
)
|
||||
|
||||
toolchain(
|
||||
name = "bsc_nixpkgs_toolchain",
|
||||
exec_compatible_with = [
|
||||
"@platforms//os:linux",
|
||||
],
|
||||
toolchain = ":bsc_nixpkgs",
|
||||
toolchain_type = "@qfc//build/bluespec:toolchain_type",
|
||||
)
|
||||
""",
|
||||
)
|
||||
|
||||
nixpkgs_package(
|
||||
name = "yosysflow",
|
||||
repositories = { "nixpkgs": "@nixpkgs//:default.nix" },
|
||||
nix_file_content = """
|
||||
with import <nixpkgs> {}; symlinkJoin {
|
||||
name = "yosysflow";
|
||||
paths = with pkgs; [ yosys nextpnr trellis ];
|
||||
}
|
||||
""",
|
||||
build_file_content = """
|
||||
load("@qfc//build:utils.bzl", "external_binary_tool")
|
||||
load("@qfc//build/synthesis:rules.bzl", "yosysflow_toolchain")
|
||||
|
||||
external_binary_tool(
|
||||
name = "yosys",
|
||||
bin = "bin/yosys",
|
||||
deps = glob([
|
||||
"bin/yosys-*",
|
||||
"share/yosys/**",
|
||||
]),
|
||||
)
|
||||
|
||||
external_binary_tool(
|
||||
name = "nextpnr_ecp5",
|
||||
bin = "bin/nextpnr-ecp5",
|
||||
deps = [],
|
||||
)
|
||||
|
||||
external_binary_tool(
|
||||
name = "ecppack",
|
||||
bin = "bin/ecppack",
|
||||
deps = [],
|
||||
)
|
||||
|
||||
yosysflow_toolchain(
|
||||
name = "yosysflow_nixpkgs_ecp5",
|
||||
yosys = ":yosys",
|
||||
nextpnr = ":nextpnr_ecp5",
|
||||
packer = ":ecppack",
|
||||
)
|
||||
|
||||
toolchain(
|
||||
name = "yosysflow_nixpkgs_ecp5_toolchain",
|
||||
exec_compatible_with = [
|
||||
"@platforms//os:linux",
|
||||
],
|
||||
target_compatible_with = [
|
||||
"@qfc//build/platforms:ecp5",
|
||||
],
|
||||
toolchain = ":yosysflow_nixpkgs_ecp5",
|
||||
toolchain_type = "@qfc//build/synthesis:toolchain_type",
|
||||
)
|
||||
""",
|
||||
)
|
||||
|
||||
register_toolchains(
|
||||
"@bluespec//:bsc_nixpkgs_toolchain",
|
||||
"@yosysflow//:yosysflow_nixpkgs_ecp5_toolchain",
|
||||
)
|
|
@ -0,0 +1,5 @@
|
|||
toolchain_type(
|
||||
name = "toolchain_type",
|
||||
visibility = ["//visibility:public"],
|
||||
)
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
load("//build:providers.bzl", "BscInfo", "VerilogInfo", "BluespecInfo")
|
||||
|
||||
def _bluespec_toolchain_impl(ctx):
|
||||
toolchain_info = platform_common.ToolchainInfo(
|
||||
bscinfo = BscInfo(
|
||||
bsc = ctx.attr.bsc,
|
||||
verilog_lib = VerilogInfo(
|
||||
sources = depset(ctx.files.verilog_lib),
|
||||
),
|
||||
),
|
||||
)
|
||||
return [toolchain_info]
|
||||
|
||||
bluespec_toolchain = rule(
|
||||
implementation = _bluespec_toolchain_impl,
|
||||
attrs = {
|
||||
"bsc": attr.label(
|
||||
executable = True,
|
||||
cfg = "exec",
|
||||
),
|
||||
"verilog_lib": attr.label_list(
|
||||
allow_files = True,
|
||||
),
|
||||
},
|
||||
)
|
||||
|
||||
def _compile(ctx, src, dep_objs, output, verilog=False, verilog_outputs=[]):
|
||||
info = ctx.toolchains["//build/bluespec:toolchain_type"].bscinfo
|
||||
bsc = info.bsc[DefaultInfo].files_to_run
|
||||
|
||||
pkg_path_set = {}
|
||||
for obj in dep_objs.to_list():
|
||||
pkg_path_set[obj.dirname] = True
|
||||
pkg_path = ['+'] + pkg_path_set.keys()
|
||||
|
||||
bdir = output.dirname
|
||||
arguments = [
|
||||
"-bdir", bdir,
|
||||
"-p", ":".join(pkg_path),
|
||||
"-q",
|
||||
]
|
||||
mnemonic = "BluespecPartialCompile"
|
||||
if verilog:
|
||||
mnemonic = "BluespecVerilogCompile"
|
||||
vdir = bdir
|
||||
if len(verilog_outputs) > 0:
|
||||
vdir = verilog_outputs[0].dirname
|
||||
arguments += [
|
||||
"-verilog",
|
||||
"-vdir", vdir,
|
||||
]
|
||||
arguments += [
|
||||
src.path,
|
||||
]
|
||||
|
||||
ctx.actions.run(
|
||||
mnemonic = mnemonic,
|
||||
executable = bsc,
|
||||
arguments = arguments,
|
||||
inputs = depset([ src ], transitive=[dep_objs]),
|
||||
outputs = verilog_outputs + [ output ],
|
||||
)
|
||||
|
||||
|
||||
def _bluespec_library_impl(ctx):
|
||||
info = ctx.toolchains["//build/bluespec:toolchain_type"].bscinfo
|
||||
bsc = info.bsc[DefaultInfo].files_to_run
|
||||
|
||||
package_order = []
|
||||
package_to_src = {}
|
||||
package_to_partial_obj = {}
|
||||
package_to_verilog_obj = {}
|
||||
package_to_verilog_modules = {}
|
||||
|
||||
for src in ctx.files.srcs:
|
||||
basename = src.basename
|
||||
if not basename.endswith(".bsv"):
|
||||
fail("Source {} invalid: does not end in .bsv".format(basename))
|
||||
package = basename[:-4]
|
||||
|
||||
package_order.append(package)
|
||||
package_to_src[package] = src
|
||||
partial_obj_name = "{}.partial/{}.bo".format(ctx.attr.name, package)
|
||||
verilog_obj_name = "{}.verilog/{}.bo".format(ctx.attr.name, package)
|
||||
package_to_partial_obj[package] = ctx.actions.declare_file(partial_obj_name)
|
||||
package_to_verilog_obj[package] = ctx.actions.declare_file(verilog_obj_name)
|
||||
|
||||
|
||||
for package, modules in ctx.attr.synthesize.items():
|
||||
if package not in package_to_src:
|
||||
fail("Package {} (in synthesize) does not exist in srcs".format(package))
|
||||
package_to_verilog_modules[package] = []
|
||||
for module in modules:
|
||||
verilog_name = "{}/{}.v".format(package, module)
|
||||
verilog = ctx.actions.declare_file(verilog_name)
|
||||
package_to_verilog_modules[package].append(verilog)
|
||||
|
||||
|
||||
input_partial_objects = depset(direct=[], transitive=[
|
||||
dep[BluespecInfo].partial_objects
|
||||
for dep in ctx.attr.deps
|
||||
])
|
||||
input_verilog_objects = depset(direct=[], transitive=[
|
||||
dep[BluespecInfo].verilog_objects
|
||||
for dep in ctx.attr.deps
|
||||
])
|
||||
|
||||
cur_partial_objs = input_partial_objects
|
||||
cur_verilog_objs = input_verilog_objects
|
||||
|
||||
for package in package_order:
|
||||
src = package_to_src[package]
|
||||
partial_obj = package_to_partial_obj[package]
|
||||
verilog_obj = package_to_verilog_obj[package]
|
||||
modules = package_to_verilog_modules.get(package, [])
|
||||
|
||||
_compile(
|
||||
ctx = ctx,
|
||||
src = src,
|
||||
dep_objs = cur_partial_objs,
|
||||
output = partial_obj,
|
||||
verilog = False,
|
||||
)
|
||||
_compile(
|
||||
ctx = ctx,
|
||||
src = src,
|
||||
dep_objs = cur_verilog_objs,
|
||||
output = verilog_obj,
|
||||
verilog = True,
|
||||
verilog_outputs = modules,
|
||||
)
|
||||
|
||||
cur_partial_objs = depset([ partial_obj ], transitive=[cur_partial_objs])
|
||||
cur_verilog_objs = depset([ verilog_obj ], transitive=[cur_verilog_objs])
|
||||
|
||||
|
||||
verilog_modules = []
|
||||
for modules in package_to_verilog_modules.values():
|
||||
verilog_modules += modules
|
||||
|
||||
return [
|
||||
DefaultInfo(
|
||||
files=depset(
|
||||
package_to_partial_obj.values() +
|
||||
package_to_verilog_obj.values() +
|
||||
verilog_modules
|
||||
)
|
||||
),
|
||||
BluespecInfo(
|
||||
partial_objects = depset(
|
||||
package_to_partial_obj.values(),
|
||||
transitive = [ input_partial_objects ],
|
||||
),
|
||||
verilog_objects = depset(
|
||||
package_to_verilog_obj.values(),
|
||||
transitive = [ input_verilog_objects ],
|
||||
),
|
||||
),
|
||||
VerilogInfo(
|
||||
sources = depset(
|
||||
verilog_modules,
|
||||
transitive = [dep[VerilogInfo].sources for dep in ctx.attr.deps] + [
|
||||
info.verilog_lib.sources
|
||||
],
|
||||
),
|
||||
),
|
||||
]
|
||||
|
||||
bluespec_library = rule(
|
||||
implementation = _bluespec_library_impl,
|
||||
attrs = {
|
||||
"srcs": attr.label_list(allow_files = True),
|
||||
"deps": attr.label_list(
|
||||
providers = [BluespecInfo, VerilogInfo],
|
||||
),
|
||||
"synthesize": attr.string_list_dict(),
|
||||
},
|
||||
toolchains = ["//build/bluespec:toolchain_type"]
|
||||
)
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
package(
|
||||
default_visibility = ["//visibility:public"],
|
||||
)
|
||||
|
||||
constraint_setting(name = "fpga_family")
|
||||
|
||||
constraint_value(
|
||||
name = "ecp5",
|
||||
constraint_setting = ":fpga_family",
|
||||
)
|
||||
|
||||
constraint_value(
|
||||
name = "ice40",
|
||||
constraint_setting = ":fpga_family",
|
||||
)
|
||||
|
||||
constraint_setting(name = "ecp5_device_type")
|
||||
|
||||
constraint_value(
|
||||
name = "LFE5U_12F",
|
||||
constraint_setting = ":ecp5_device_type",
|
||||
)
|
||||
|
||||
constraint_setting(name = "ecp5_package")
|
||||
|
||||
constraint_value(
|
||||
name = "CABGA381",
|
||||
constraint_setting = ":ecp5_package",
|
||||
)
|
||||
|
||||
constraint_setting(name = "board")
|
||||
|
||||
constraint_value(
|
||||
name = "ulx3s",
|
||||
constraint_setting = ":board",
|
||||
)
|
||||
|
||||
platform(
|
||||
name = "ulx3s_12f",
|
||||
constraint_values = [
|
||||
"@platforms//os:none",
|
||||
":ecp5",
|
||||
":LFE5U_12F",
|
||||
":CABGA381",
|
||||
":ulx3s",
|
||||
],
|
||||
)
|
|
@ -0,0 +1,33 @@
|
|||
# Bluespec Compiler provider, used by Bluespec Toolchain.
|
||||
BscInfo = provider(
|
||||
fields = [
|
||||
"bsc",
|
||||
"verilog_lib",
|
||||
],
|
||||
)
|
||||
|
||||
YosysFlowInfo = provider(
|
||||
fields = [
|
||||
"yosys",
|
||||
"nextpnr",
|
||||
"packer",
|
||||
|
||||
"synth_command",
|
||||
],
|
||||
)
|
||||
|
||||
# Bluespec intermediary compilation data.
|
||||
BluespecInfo = provider(
|
||||
fields = [
|
||||
"partial_objects",
|
||||
"verilog_objects",
|
||||
],
|
||||
)
|
||||
|
||||
# Verilog module sources.
|
||||
VerilogInfo = provider(
|
||||
fields = [
|
||||
"sources",
|
||||
],
|
||||
)
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
toolchain_type(
|
||||
name = "toolchain_type",
|
||||
visibility = ["//visibility:public"],
|
||||
)
|
||||
|
|
@ -0,0 +1,148 @@
|
|||
load("//build:providers.bzl", "YosysFlowInfo", "VerilogInfo")
|
||||
|
||||
def _yosysflow_toolchain_impl(ctx):
|
||||
toolchain_info = platform_common.ToolchainInfo(
|
||||
yosysflowinfo = YosysFlowInfo(
|
||||
yosys = ctx.attr.yosys,
|
||||
nextpnr = ctx.attr.nextpnr,
|
||||
packer = ctx.attr.packer,
|
||||
),
|
||||
)
|
||||
return [toolchain_info]
|
||||
|
||||
|
||||
yosysflow_toolchain = rule(
|
||||
implementation = _yosysflow_toolchain_impl,
|
||||
attrs = {
|
||||
"yosys": attr.label(
|
||||
executable = True,
|
||||
cfg = "exec",
|
||||
),
|
||||
"nextpnr": attr.label(
|
||||
executable = True,
|
||||
cfg = "exec",
|
||||
),
|
||||
"packer": attr.label(
|
||||
executable = True,
|
||||
cfg = "exec",
|
||||
),
|
||||
},
|
||||
)
|
||||
|
||||
def _is_set(ctx, attr):
|
||||
constraint = attr[platform_common.ConstraintValueInfo]
|
||||
return ctx.target_platform_has_constraint(constraint)
|
||||
|
||||
def _get_flags(ctx):
|
||||
if _is_set(ctx, ctx.attr._fpga_family_ecp5):
|
||||
nextpnr_flags = [
|
||||
"--lpf", "%CONSTRAINT_FILE%",
|
||||
"--json", "%JSON_FILE%",
|
||||
"--textcfg", "%OUT_FILE%",
|
||||
]
|
||||
if _is_set(ctx, ctx.attr._ecp5_lfe5u_12f):
|
||||
nextpnr_flags.append("--12k")
|
||||
if _is_set(ctx, ctx.attr._ecp5_cabga381):
|
||||
nextpnr_flags += ["--package", "CABGA381"]
|
||||
|
||||
return struct(
|
||||
yosys_synth_command = "synth_ecp5 -top %TOP%",
|
||||
nextpnr_flags = nextpnr_flags,
|
||||
)
|
||||
fail("Unsupported FPGA (needs //build/platforms:fpga_family constraint set)")
|
||||
|
||||
def _yosysflow_bitstream_impl(ctx):
|
||||
info = ctx.toolchains["//build/synthesis:toolchain_type"].yosysflowinfo
|
||||
yosys = info.yosys[DefaultInfo].files_to_run
|
||||
nextpnr = info.nextpnr[DefaultInfo].files_to_run
|
||||
packer = info.packer[DefaultInfo].files_to_run
|
||||
flags = _get_flags(ctx)
|
||||
|
||||
sources = depset(
|
||||
ctx.files.srcs,
|
||||
transitive = [dep[VerilogInfo].sources for dep in ctx.attr.deps],
|
||||
)
|
||||
|
||||
srcline = " ".join([s.path for s in sources.to_list()])
|
||||
synth_command = flags.yosys_synth_command.replace('%TOP%', ctx.attr.top)
|
||||
|
||||
json = ctx.actions.declare_file(ctx.attr.name + ".json")
|
||||
scriptfile = ctx.actions.declare_file(ctx.attr.name + ".ys")
|
||||
ctx.actions.write(
|
||||
output = scriptfile,
|
||||
content = """
|
||||
read_verilog {}
|
||||
{}
|
||||
write_json {}
|
||||
""".format(
|
||||
srcline,
|
||||
synth_command,
|
||||
json.path,
|
||||
),
|
||||
)
|
||||
|
||||
ctx.actions.run(
|
||||
mnemonic = "DesignSynthesize",
|
||||
executable = yosys,
|
||||
arguments = [
|
||||
"-s", scriptfile.path,
|
||||
"-q",
|
||||
],
|
||||
inputs = depset([ scriptfile ], transitive=[ sources ]),
|
||||
outputs = [ json ],
|
||||
)
|
||||
|
||||
unpacked = ctx.actions.declare_file(ctx.attr.name + ".pnr")
|
||||
|
||||
nextpnr_arguments = [
|
||||
(f
|
||||
.replace("%CONSTRAINT_FILE%", ctx.file.constraints.path)
|
||||
.replace("%JSON_FILE%", json.path)
|
||||
.replace("%OUT_FILE%", unpacked.path)
|
||||
)
|
||||
for f in flags.nextpnr_flags
|
||||
]
|
||||
|
||||
ctx.actions.run(
|
||||
mnemonic = "BitstreamRoute",
|
||||
executable = nextpnr,
|
||||
arguments = nextpnr_arguments + [ "-q" ],
|
||||
inputs = [ json, ctx.file.constraints ],
|
||||
outputs = [ unpacked ],
|
||||
)
|
||||
|
||||
packed = ctx.actions.declare_file(ctx.attr.name + ".bit")
|
||||
|
||||
ctx.actions.run(
|
||||
mnemonic = "BitstreamPack",
|
||||
executable = packer,
|
||||
arguments = [ unpacked.path, packed.path ],
|
||||
inputs = [ unpacked ],
|
||||
outputs = [ packed ],
|
||||
)
|
||||
|
||||
return [
|
||||
DefaultInfo(
|
||||
files = depset([packed]),
|
||||
)
|
||||
]
|
||||
|
||||
yosysflow_bitstream = rule(
|
||||
implementation = _yosysflow_bitstream_impl,
|
||||
attrs = {
|
||||
"srcs": attr.label_list(
|
||||
allow_files = True,
|
||||
),
|
||||
"deps": attr.label_list(
|
||||
providers = [VerilogInfo],
|
||||
),
|
||||
"top": attr.string(),
|
||||
"constraints": attr.label(allow_single_file = True),
|
||||
|
||||
"_fpga_family_ecp5": attr.label(default="//build/platforms:ecp5"),
|
||||
"_fpga_family_ice40": attr.label(default="//build/platforms:ice40"),
|
||||
"_ecp5_lfe5u_12f": attr.label(default="//build/platforms:LFE5U_12F"),
|
||||
"_ecp5_cabga381": attr.label(default="//build/platforms:CABGA381"),
|
||||
},
|
||||
toolchains = ["//build/synthesis:toolchain_type"],
|
||||
)
|
|
@ -0,0 +1,38 @@
|
|||
def _external_binary_tool_impl(ctx):
|
||||
executable = ctx.actions.declare_file(ctx.attr.name + ".bin")
|
||||
path = ctx.file.bin.path
|
||||
strip = "external/"
|
||||
if not path.startswith(strip):
|
||||
fail("Unexpected path {}".format(path))
|
||||
path = path[len(strip):]
|
||||
ctx.actions.write(
|
||||
output = executable,
|
||||
content = """#!/usr/bin/env sh
|
||||
sp="{}"
|
||||
bin=$0.runfiles/$sp
|
||||
exec $bin $@
|
||||
""".format(path),
|
||||
is_executable = True,
|
||||
)
|
||||
|
||||
files = depset([executable])
|
||||
runfiles = ctx.runfiles(files = [ctx.file.bin, executable] + ctx.files.deps)
|
||||
res = [
|
||||
DefaultInfo(files=files, runfiles=runfiles, executable=executable),
|
||||
]
|
||||
return res
|
||||
|
||||
external_binary_tool = rule(
|
||||
implementation = _external_binary_tool_impl,
|
||||
attrs = {
|
||||
"bin": attr.label(
|
||||
executable = True,
|
||||
allow_single_file = True,
|
||||
cfg = "exec",
|
||||
),
|
||||
"deps": attr.label_list(
|
||||
allow_files = True,
|
||||
),
|
||||
},
|
||||
)
|
||||
|
Loading…
Reference in New Issue