843 lines
23 KiB
C
843 lines
23 KiB
C
/******************************************************************************
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*
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* (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved.
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*
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* Module: HalRf6052.c ( Source C File)
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*
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* Note: Provide RF 6052 series relative API.
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*
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* Function:
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*
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* Export:
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*
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* Abbrev:
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*
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* History:
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* Data Who Remark
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*
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* 09/25/2008 MHC Create initial version.
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* 11/05/2008 MHC Add API for tw power setting.
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*
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*
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******************************************************************************/
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#include "r8192U.h"
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#include "r8192S_rtl6052.h"
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#include "r8192S_hw.h"
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#include "r8192S_phyreg.h"
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#include "r8192S_phy.h"
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/*---------------------------Define Local Constant---------------------------*/
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// Define local structure for debug!!!!!
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typedef struct RF_Shadow_Compare_Map {
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// Shadow register value
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u32 Value;
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// Compare or not flag
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u8 Compare;
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// Record If it had ever modified unpredicted
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u8 ErrorOrNot;
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// Recorver Flag
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u8 Recorver;
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//
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u8 Driver_Write;
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}RF_SHADOW_T;
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/*---------------------------Define Local Constant---------------------------*/
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/*------------------------Define global variable-----------------------------*/
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/*------------------------Define global variable-----------------------------*/
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/*---------------------Define local function prototype-----------------------*/
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void phy_RF6052_Config_HardCode(struct net_device* dev);
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RT_STATUS phy_RF6052_Config_ParaFile(struct net_device* dev);
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/*---------------------Define local function prototype-----------------------*/
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/*------------------------Define function prototype--------------------------*/
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extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate);
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/*------------------------Define function prototype--------------------------*/
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/*------------------------Define local variable------------------------------*/
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// 2008/11/20 MH For Debug only, RF
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static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];// = {{0}};//FIXLZM
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/*------------------------Define local variable------------------------------*/
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/*------------------------Define function prototype--------------------------*/
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/*-----------------------------------------------------------------------------
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* Function: RF_ChangeTxPath
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*
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* Overview: For RL6052, we must change some RF settign for 1T or 2T.
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*
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* Input: u16 DataRate // 0x80-8f, 0x90-9f
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*
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* Output: NONE
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*
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* Return: NONE
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*
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* Revised History:
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* When Who Remark
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* 09/25/2008 MHC Create Version 0.
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* Firmwaer support the utility later.
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*
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*---------------------------------------------------------------------------*/
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extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate)
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{
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} /* RF_ChangeTxPath */
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/*-----------------------------------------------------------------------------
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* Function: PHY_RF6052SetBandwidth()
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*
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* Overview: This function is called by SetBWModeCallback8190Pci() only
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*
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* Input: PADAPTER Adapter
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* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
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*
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* Output: NONE
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*
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* Return: NONE
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*
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* Note: For RF type 0222D
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*---------------------------------------------------------------------------*/
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void PHY_RF6052SetBandwidth(struct net_device* dev, HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
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{
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//u8 eRFPath;
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//struct r8192_priv *priv = ieee80211_priv(dev);
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//if (priv->card_8192 == NIC_8192SE)
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{
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switch(Bandwidth)
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{
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case HT_CHANNEL_WIDTH_20:
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//if (priv->card_8192_version >= VERSION_8192S_BCUT)
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// rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
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rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01);
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break;
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case HT_CHANNEL_WIDTH_20_40:
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//if (priv->card_8192_version >= VERSION_8192S_BCUT)
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// rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
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rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00);
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break;
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default:
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RT_TRACE(COMP_DBG, "PHY_SetRF6052Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth);
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break;
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}
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}
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// else
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}
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/*-----------------------------------------------------------------------------
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* Function: PHY_RF6052SetCckTxPower
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*
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* Overview:
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*
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* Input: NONE
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*
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* Output: NONE
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*
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* Return: NONE
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*
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* Revised History:
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* When Who Remark
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* 11/05/2008 MHC Simulate 8192series..
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*
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*---------------------------------------------------------------------------*/
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extern void PHY_RF6052SetCckTxPower(struct net_device* dev, u8 powerlevel)
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{
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struct r8192_priv *priv = ieee80211_priv(dev);
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u32 TxAGC=0;
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if(priv->ieee80211->scanning == 1)
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TxAGC = 0x3f;
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else if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range
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TxAGC = 0x22;
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else
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TxAGC = powerlevel;
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//cosa add for lenovo, to pass the safety spec, don't increase power index for different rates.
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if(priv->bIgnoreDiffRateTxPowerOffset)
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TxAGC = powerlevel;
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if(TxAGC > RF6052_MAX_TX_PWR)
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TxAGC = RF6052_MAX_TX_PWR;
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//printk("CCK PWR= %x\n", TxAGC);
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rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
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} /* PHY_RF6052SetCckTxPower */
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/*-----------------------------------------------------------------------------
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* Function: PHY_RF6052SetOFDMTxPower
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*
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* Overview: For legacy and HY OFDM, we must read EEPROM TX power index for
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* different channel and read original value in TX power register area from
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* 0xe00. We increase offset and original value to be correct tx pwr.
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*
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* Input: NONE
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*
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* Output: NONE
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*
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* Return: NONE
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*
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* Revised History:
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* When Who Remark
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* 11/05/2008 MHC Simulate 8192 series method.
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* 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to
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* A/B pwr difference or legacy/HT pwr diff.
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* 2. We concern with path B legacy/HT OFDM difference.
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* 01/22/2009 MHC Support new EPRO format from SD3.
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*---------------------------------------------------------------------------*/
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#if 1
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extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel)
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{
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struct r8192_priv *priv = ieee80211_priv(dev);
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u32 writeVal, powerBase0, powerBase1;
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u8 index = 0;
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u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
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//u8 byte0, byte1, byte2, byte3;
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u8 Channel = priv->ieee80211->current_network.channel;
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u8 rfa_pwr[4];
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u8 rfa_lower_bound = 0, rfa_upper_bound = 0 /*, rfa_htpwr, rfa_legacypwr*/;
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u8 i;
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u8 rf_pwr_diff = 0;
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u8 Legacy_pwrdiff=0, HT20_pwrdiff=0, BandEdge_Pwrdiff=0;
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u8 ofdm_bandedge_chnl_low=0, ofdm_bandedge_chnl_high=0;
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// We only care about the path A for legacy.
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if (priv->EEPROMVersion != 2)
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powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf);
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else if (priv->EEPROMVersion == 2) // Defined by SD1 Jong
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{
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//
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// 2009/01/21 MH Support new EEPROM format from SD3 requirement
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//
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Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][Channel-1];
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// For legacy OFDM, tx pwr always > HT OFDM pwr. We do not care Path B
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// legacy OFDM pwr diff. NO BB register to notify HW.
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powerBase0 = powerlevel + Legacy_pwrdiff;
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//RTPRINT(FPHY, PHY_TXPWR, (" [LagacyToHT40 pwr diff = %d]\n", Legacy_pwrdiff));
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// Band Edge scheme is enabled for FCC mode
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if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
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{
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ofdm_bandedge_chnl_low = 1;
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ofdm_bandedge_chnl_high = 11;
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BandEdge_Pwrdiff = 0;
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if (Channel <= ofdm_bandedge_chnl_low)
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BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0];
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else if (Channel >= ofdm_bandedge_chnl_high)
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{
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BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1];
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}
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powerBase0 -= BandEdge_Pwrdiff;
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if (Channel <= ofdm_bandedge_chnl_low || Channel >= ofdm_bandedge_chnl_high)
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{
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//RTPRINT(FPHY, PHY_TXPWR, (" [OFDM band-edge channel = %d, pwr diff = %d]\n",
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//Channel, BandEdge_Pwrdiff));
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}
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}
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//RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index = 0x%x]\n", powerBase0));
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}
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powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
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//MCS rates
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if(priv->EEPROMVersion == 2)
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{
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//Cosa add for new EEPROM content. 02102009
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//Check HT20 to HT40 diff
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if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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{
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// HT 20<->40 pwr diff
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HT20_pwrdiff = priv->TxPwrHt20Diff[RF90_PATH_A][Channel-1];
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// Calculate Antenna pwr diff
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if (HT20_pwrdiff < 8) // 0~+7
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powerlevel += HT20_pwrdiff;
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else // index8-15=-8~-1
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powerlevel -= (16-HT20_pwrdiff);
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//RTPRINT(FPHY, PHY_TXPWR, (" [HT20 to HT40 pwrdiff = %d]\n", HT20_pwrdiff));
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//RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index = 0x%x]\n", powerlevel));
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}
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// Band Edge scheme is enabled for FCC mode
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if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
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{
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BandEdge_Pwrdiff = 0;
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if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
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{
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if (Channel <= 3)
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BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][0];
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else if (Channel >= 9)
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BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][1];
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if (Channel <= 3 || Channel >= 9)
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{
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//RTPRINT(FPHY, PHY_TXPWR, (" [HT40 band-edge channel = %d, pwr diff = %d]\n",
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//Channel, BandEdge_Pwrdiff));
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}
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}
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else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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{
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if (Channel <= 1)
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BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][0];
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else if (Channel >= 11)
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BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][1];
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if (Channel <= 1 || Channel >= 11)
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{
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//RTPRINT(FPHY, PHY_TXPWR, (" [HT20 band-edge channel = %d, pwr diff = %d]\n",
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//Channel, BandEdge_Pwrdiff));
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}
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}
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powerlevel -= BandEdge_Pwrdiff;
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//RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index = 0x%x]\n", powerlevel));
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}
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}
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powerBase1 = powerlevel;
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powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
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//RTPRINT(FPHY, PHY_TXPWR, (" [Legacy/HT power index= %x/%x]\n", powerBase0, powerBase1));
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for(index=0; index<6; index++)
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{
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//
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// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
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//
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//cosa add for lenovo, to pass the safety spec, don't increase power index for different rates.
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if(priv->bIgnoreDiffRateTxPowerOffset)
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writeVal = ((index<2)?powerBase0:powerBase1);
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else
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writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1);
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//RTPRINT(FPHY, PHY_TXPWR, ("Reg 0x%x, Original=%x writeVal=%x\n",
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//RegOffset[index], priv->MCSTxPowerLevelOriginalOffset[index], writeVal));
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//
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// If path A and Path B coexist, we must limit Path A tx power.
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// Protect Path B pwr over or underflow. We need to calculate upper and
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// lower bound of path A tx power.
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//
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if (priv->rf_type == RF_2T2R)
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{
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rf_pwr_diff = priv->AntennaTxPwDiff[0];
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//RTPRINT(FPHY, PHY_TXPWR, ("2T2R RF-B to RF-A PWR DIFF=%d\n", rf_pwr_diff));
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if (rf_pwr_diff >= 8) // Diff=-8~-1
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{ // Prevent underflow!!
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rfa_lower_bound = 0x10-rf_pwr_diff;
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//RTPRINT(FPHY, PHY_TXPWR, ("rfa_lower_bound= %d\n", rfa_lower_bound));
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}
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else if (rf_pwr_diff >= 0) // Diff = 0-7
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{
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rfa_upper_bound = RF6052_MAX_TX_PWR-rf_pwr_diff;
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//RTPRINT(FPHY, PHY_TXPWR, ("rfa_upper_bound= %d\n", rfa_upper_bound));
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}
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}
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for (i= 0; i <4; i++)
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{
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rfa_pwr[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
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if (rfa_pwr[i] > RF6052_MAX_TX_PWR)
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rfa_pwr[i] = RF6052_MAX_TX_PWR;
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//
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// If path A and Path B coexist, we must limit Path A tx power.
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// Protect Path B pwr under/over flow. We need to calculate upper and
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// lower bound of path A tx power.
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//
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if (priv->rf_type == RF_2T2R)
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{
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if (rf_pwr_diff >= 8) // Diff=-8~-1
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{ // Prevent underflow!!
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if (rfa_pwr[i] <rfa_lower_bound)
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{
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//RTPRINT(FPHY, PHY_TXPWR, ("Underflow"));
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rfa_pwr[i] = rfa_lower_bound;
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}
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}
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else if (rf_pwr_diff >= 1) // Diff = 0-7
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{ // Prevent overflow
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if (rfa_pwr[i] > rfa_upper_bound)
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{
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//RTPRINT(FPHY, PHY_TXPWR, ("Overflow"));
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rfa_pwr[i] = rfa_upper_bound;
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}
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}
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//RTPRINT(FPHY, PHY_TXPWR, ("rfa_pwr[%d]=%x\n", i, rfa_pwr[i]));
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}
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}
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//
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// Add description: PWDB > threshold!!!High power issue!!
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// We must decrease tx power !! Why is the value ???
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//
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if(priv->bDynamicTxHighPower == TRUE)
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{
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// For MCS rate
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if(index > 1)
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{
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writeVal = 0x03030303;
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}
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// For Legacy rate
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else
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{
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writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0];
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}
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//RTPRINT(FPHY, PHY_TXPWR, ("HighPower=%08x\n", writeVal));
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}
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else
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{
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writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0];
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//RTPRINT(FPHY, PHY_TXPWR, ("NormalPower=%08x\n", writeVal));
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}
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//
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// Write different rate set tx power index.
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//
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//if (DCMD_Test_Flag == 0)
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rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
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}
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} /* PHY_RF6052SetOFDMTxPower */
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#else
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extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel)
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{
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struct r8192_priv *priv = ieee80211_priv(dev);
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u32 writeVal, powerBase0, powerBase1;
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u8 index = 0;
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u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
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u8 byte0, byte1, byte2, byte3;
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u8 channel = priv->ieee80211->current_network.channel;
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//Legacy OFDM rates
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powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf);
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powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
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//MCS rates HT OFDM
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powerBase1 = powerlevel;
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powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
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//printk("Legacy/HT PWR= %x/%x\n", powerBase0, powerBase1);
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for(index=0; index<6; index++)
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{
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//
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// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
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//
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writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1);
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//printk("Index = %d Original=%x writeVal=%x\n", index, priv->MCSTxPowerLevelOriginalOffset[index], writeVal);
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byte0 = (u8)(writeVal & 0x7f);
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byte1 = (u8)((writeVal & 0x7f00)>>8);
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byte2 = (u8)((writeVal & 0x7f0000)>>16);
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byte3 = (u8)((writeVal & 0x7f000000)>>24);
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// Max power index = 0x3F Range = 0-0x3F
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if(byte0 > RF6052_MAX_TX_PWR)
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byte0 = RF6052_MAX_TX_PWR;
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if(byte1 > RF6052_MAX_TX_PWR)
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byte1 = RF6052_MAX_TX_PWR;
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if(byte2 > RF6052_MAX_TX_PWR)
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byte2 = RF6052_MAX_TX_PWR;
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if(byte3 > RF6052_MAX_TX_PWR)
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byte3 = RF6052_MAX_TX_PWR;
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//
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// Add description: PWDB > threshold!!!High power issue!!
|
|
// We must decrease tx power !! Why is the value ???
|
|
//
|
|
if(priv->bDynamicTxHighPower == true)
|
|
{
|
|
// For MCS rate
|
|
if(index > 1)
|
|
{
|
|
writeVal = 0x03030303;
|
|
}
|
|
// For Legacy rate
|
|
else
|
|
{
|
|
writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
|
|
}
|
|
|
|
//
|
|
// Write different rate set tx power index.
|
|
//
|
|
rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
|
|
}
|
|
|
|
} /* PHY_RF6052SetOFDMTxPower */
|
|
#endif
|
|
|
|
RT_STATUS PHY_RF6052_Config(struct net_device* dev)
|
|
{
|
|
struct r8192_priv *priv = ieee80211_priv(dev);
|
|
RT_STATUS rtStatus = RT_STATUS_SUCCESS;
|
|
//RF90_RADIO_PATH_E eRFPath;
|
|
//BB_REGISTER_DEFINITION_T *pPhyReg;
|
|
//u32 OrgStoreRFIntSW[RF90_PATH_D+1];
|
|
|
|
//
|
|
// Initialize general global value
|
|
//
|
|
// TODO: Extend RF_PATH_C and RF_PATH_D in the future
|
|
if(priv->rf_type == RF_1T1R)
|
|
priv->NumTotalRFPath = 1;
|
|
else
|
|
priv->NumTotalRFPath = 2;
|
|
|
|
//
|
|
// Config BB and RF
|
|
//
|
|
// switch( priv->bRegHwParaFile )
|
|
// {
|
|
// case 0:
|
|
// phy_RF6052_Config_HardCode(dev);
|
|
// break;
|
|
|
|
// case 1:
|
|
rtStatus = phy_RF6052_Config_ParaFile(dev);
|
|
// break;
|
|
|
|
// case 2:
|
|
// Partial Modify.
|
|
// phy_RF6052_Config_HardCode(dev);
|
|
// phy_RF6052_Config_ParaFile(dev);
|
|
// break;
|
|
|
|
// default:
|
|
// phy_RF6052_Config_HardCode(dev);
|
|
// break;
|
|
// }
|
|
return rtStatus;
|
|
|
|
}
|
|
|
|
void phy_RF6052_Config_HardCode(struct net_device* dev)
|
|
{
|
|
|
|
// Set Default Bandwidth to 20M
|
|
//Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20);
|
|
|
|
// TODO: Set Default Channel to channel one for RTL8225
|
|
|
|
}
|
|
|
|
RT_STATUS phy_RF6052_Config_ParaFile(struct net_device* dev)
|
|
{
|
|
u32 u4RegValue = 0;
|
|
//static s1Byte szRadioAFile[] = RTL819X_PHY_RADIO_A;
|
|
//static s1Byte szRadioBFile[] = RTL819X_PHY_RADIO_B;
|
|
//static s1Byte szRadioBGMFile[] = RTL819X_PHY_RADIO_B_GM;
|
|
u8 eRFPath;
|
|
RT_STATUS rtStatus = RT_STATUS_SUCCESS;
|
|
struct r8192_priv *priv = ieee80211_priv(dev);
|
|
BB_REGISTER_DEFINITION_T *pPhyReg;
|
|
//u8 eCheckItem;
|
|
|
|
|
|
//3//-----------------------------------------------------------------
|
|
//3// <2> Initialize RF
|
|
//3//-----------------------------------------------------------------
|
|
//for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
|
|
for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
|
|
{
|
|
|
|
pPhyReg = &priv->PHYRegDef[eRFPath];
|
|
|
|
/*----Store original RFENV control type----*/
|
|
switch(eRFPath)
|
|
{
|
|
case RF90_PATH_A:
|
|
case RF90_PATH_C:
|
|
u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
|
|
break;
|
|
case RF90_PATH_B :
|
|
case RF90_PATH_D:
|
|
u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
|
|
break;
|
|
}
|
|
|
|
/*----Set RF_ENV enable----*/
|
|
rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
|
|
|
|
/*----Set RF_ENV output high----*/
|
|
rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
|
|
|
|
/* Set bit number of Address and Data for RF register */
|
|
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
|
|
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
|
|
|
|
|
|
/*----Initialize RF fom connfiguration file----*/
|
|
switch(eRFPath)
|
|
{
|
|
case RF90_PATH_A:
|
|
rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
|
|
break;
|
|
case RF90_PATH_B:
|
|
rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
|
|
break;
|
|
case RF90_PATH_C:
|
|
break;
|
|
case RF90_PATH_D:
|
|
break;
|
|
}
|
|
|
|
/*----Restore RFENV control type----*/;
|
|
switch(eRFPath)
|
|
{
|
|
case RF90_PATH_A:
|
|
case RF90_PATH_C:
|
|
rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
|
|
break;
|
|
case RF90_PATH_B :
|
|
case RF90_PATH_D:
|
|
rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
|
|
break;
|
|
}
|
|
|
|
if(rtStatus != RT_STATUS_SUCCESS){
|
|
printk("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
|
|
goto phy_RF6052_Config_ParaFile_Fail;
|
|
}
|
|
|
|
}
|
|
|
|
RT_TRACE(COMP_INIT, "<---phy_RF6052_Config_ParaFile()\n");
|
|
return rtStatus;
|
|
|
|
phy_RF6052_Config_ParaFile_Fail:
|
|
return rtStatus;
|
|
}
|
|
|
|
|
|
//
|
|
// ==> RF shadow Operation API Code Section!!!
|
|
//
|
|
/*-----------------------------------------------------------------------------
|
|
* Function: PHY_RFShadowRead
|
|
* PHY_RFShadowWrite
|
|
* PHY_RFShadowCompare
|
|
* PHY_RFShadowRecorver
|
|
* PHY_RFShadowCompareAll
|
|
* PHY_RFShadowRecorverAll
|
|
* PHY_RFShadowCompareFlagSet
|
|
* PHY_RFShadowRecorverFlagSet
|
|
*
|
|
* Overview: When we set RF register, we must write shadow at first.
|
|
* When we are running, we must compare shadow abd locate error addr.
|
|
* Decide to recorver or not.
|
|
*
|
|
* Input: NONE
|
|
*
|
|
* Output: NONE
|
|
*
|
|
* Return: NONE
|
|
*
|
|
* Revised History:
|
|
* When Who Remark
|
|
* 11/20/2008 MHC Create Version 0.
|
|
*
|
|
*---------------------------------------------------------------------------*/
|
|
extern u32 PHY_RFShadowRead(
|
|
struct net_device * dev,
|
|
RF90_RADIO_PATH_E eRFPath,
|
|
u32 Offset)
|
|
{
|
|
return RF_Shadow[eRFPath][Offset].Value;
|
|
|
|
} /* PHY_RFShadowRead */
|
|
|
|
|
|
extern void PHY_RFShadowWrite(
|
|
struct net_device * dev,
|
|
u32 eRFPath,
|
|
u32 Offset,
|
|
u32 Data)
|
|
{
|
|
//RF_Shadow[eRFPath][Offset].Value = (Data & bMask20Bits);
|
|
RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask);
|
|
RF_Shadow[eRFPath][Offset].Driver_Write = true;
|
|
|
|
} /* PHY_RFShadowWrite */
|
|
|
|
|
|
extern void PHY_RFShadowCompare(
|
|
struct net_device * dev,
|
|
RF90_RADIO_PATH_E eRFPath,
|
|
u32 Offset)
|
|
{
|
|
u32 reg;
|
|
|
|
// Check if we need to check the register
|
|
if (RF_Shadow[eRFPath][Offset].Compare == true)
|
|
{
|
|
reg = rtl8192_phy_QueryRFReg(dev, eRFPath, Offset, bRFRegOffsetMask);
|
|
// Compare shadow and real rf register for 20bits!!
|
|
if (RF_Shadow[eRFPath][Offset].Value != reg)
|
|
{
|
|
// Locate error position.
|
|
RF_Shadow[eRFPath][Offset].ErrorOrNot = true;
|
|
RT_TRACE(COMP_INIT, "PHY_RFShadowCompare RF-%d Addr%02xErr = %05x", eRFPath, Offset, reg);
|
|
}
|
|
}
|
|
|
|
} /* PHY_RFShadowCompare */
|
|
|
|
extern void PHY_RFShadowRecorver(
|
|
struct net_device * dev,
|
|
RF90_RADIO_PATH_E eRFPath,
|
|
u32 Offset)
|
|
{
|
|
// Check if the address is error
|
|
if (RF_Shadow[eRFPath][Offset].ErrorOrNot == true)
|
|
{
|
|
// Check if we need to recorver the register.
|
|
if (RF_Shadow[eRFPath][Offset].Recorver == true)
|
|
{
|
|
rtl8192_phy_SetRFReg(dev, eRFPath, Offset, bRFRegOffsetMask, RF_Shadow[eRFPath][Offset].Value);
|
|
RT_TRACE(COMP_INIT, "PHY_RFShadowRecorver RF-%d Addr%02x=%05x",
|
|
eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value);
|
|
}
|
|
}
|
|
|
|
} /* PHY_RFShadowRecorver */
|
|
|
|
|
|
extern void PHY_RFShadowCompareAll(struct net_device * dev)
|
|
{
|
|
u32 eRFPath;
|
|
u32 Offset;
|
|
|
|
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
|
|
{
|
|
for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
|
|
{
|
|
PHY_RFShadowCompare(dev, (RF90_RADIO_PATH_E)eRFPath, Offset);
|
|
}
|
|
}
|
|
|
|
} /* PHY_RFShadowCompareAll */
|
|
|
|
|
|
extern void PHY_RFShadowRecorverAll(struct net_device * dev)
|
|
{
|
|
u32 eRFPath;
|
|
u32 Offset;
|
|
|
|
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
|
|
{
|
|
for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
|
|
{
|
|
PHY_RFShadowRecorver(dev, (RF90_RADIO_PATH_E)eRFPath, Offset);
|
|
}
|
|
}
|
|
|
|
} /* PHY_RFShadowRecorverAll */
|
|
|
|
|
|
extern void PHY_RFShadowCompareFlagSet(
|
|
struct net_device * dev,
|
|
RF90_RADIO_PATH_E eRFPath,
|
|
u32 Offset,
|
|
u8 Type)
|
|
{
|
|
// Set True or False!!!
|
|
RF_Shadow[eRFPath][Offset].Compare = Type;
|
|
|
|
} /* PHY_RFShadowCompareFlagSet */
|
|
|
|
|
|
extern void PHY_RFShadowRecorverFlagSet(
|
|
struct net_device * dev,
|
|
RF90_RADIO_PATH_E eRFPath,
|
|
u32 Offset,
|
|
u8 Type)
|
|
{
|
|
// Set True or False!!!
|
|
RF_Shadow[eRFPath][Offset].Recorver= Type;
|
|
|
|
} /* PHY_RFShadowRecorverFlagSet */
|
|
|
|
|
|
extern void PHY_RFShadowCompareFlagSetAll(struct net_device * dev)
|
|
{
|
|
u32 eRFPath;
|
|
u32 Offset;
|
|
|
|
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
|
|
{
|
|
for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
|
|
{
|
|
// 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
|
|
if (Offset != 0x26 && Offset != 0x27)
|
|
PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, FALSE);
|
|
else
|
|
PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, TRUE);
|
|
}
|
|
}
|
|
|
|
} /* PHY_RFShadowCompareFlagSetAll */
|
|
|
|
|
|
extern void PHY_RFShadowRecorverFlagSetAll(struct net_device * dev)
|
|
{
|
|
u32 eRFPath;
|
|
u32 Offset;
|
|
|
|
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
|
|
{
|
|
for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
|
|
{
|
|
// 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
|
|
if (Offset != 0x26 && Offset != 0x27)
|
|
PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, FALSE);
|
|
else
|
|
PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, TRUE);
|
|
}
|
|
}
|
|
|
|
} /* PHY_RFShadowCompareFlagSetAll */
|
|
|
|
|
|
|
|
extern void PHY_RFShadowRefresh(struct net_device * dev)
|
|
{
|
|
u32 eRFPath;
|
|
u32 Offset;
|
|
|
|
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
|
|
{
|
|
for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
|
|
{
|
|
RF_Shadow[eRFPath][Offset].Value = 0;
|
|
RF_Shadow[eRFPath][Offset].Compare = false;
|
|
RF_Shadow[eRFPath][Offset].Recorver = false;
|
|
RF_Shadow[eRFPath][Offset].ErrorOrNot = false;
|
|
RF_Shadow[eRFPath][Offset].Driver_Write = false;
|
|
}
|
|
}
|
|
|
|
} /* PHY_RFShadowRead */
|
|
|
|
/* End of HalRf6052.c */
|