3d467676ab
More and more boards are going to start shipping that boot with the MMU in 32BIT mode by default. Previously we relied on the bootloader to setup PMB mappings for use by the kernel but we also need to cater for boards whose bootloaders don't set them up. If CONFIG_PMB_LEGACY is not enabled we have full control over our PMB mappings and can compress our address space. Usually, the distance between the the cached and uncached mappings of RAM is always 512MB, however we can compress the distance to be the amount of RAM on the board. pmb_init() now becomes much simpler. It no longer has to calculate any mappings, it just has to synchronise the software PMB table with the hardware. Tested on SDK7786 and SH7785LCR. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
376 lines
7.5 KiB
ArmAsm
376 lines
7.5 KiB
ArmAsm
/* $Id: head.S,v 1.7 2003/09/01 17:58:19 lethal Exp $
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*
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* arch/sh/kernel/head.S
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*
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* Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
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* Copyright (C) 2010 Matt Fleming
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Head.S contains the SH exception handlers and startup code.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/thread_info.h>
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#include <asm/mmu.h>
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#include <cpu/mmu_context.h>
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#ifdef CONFIG_CPU_SH4A
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#define SYNCO() synco
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#define PREFI(label, reg) \
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mov.l label, reg; \
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prefi @reg
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#else
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#define SYNCO()
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#define PREFI(label, reg)
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#endif
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.section .empty_zero_page, "aw"
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ENTRY(empty_zero_page)
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.long 1 /* MOUNT_ROOT_RDONLY */
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.long 0 /* RAMDISK_FLAGS */
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.long 0x0200 /* ORIG_ROOT_DEV */
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.long 1 /* LOADER_TYPE */
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.long 0x00000000 /* INITRD_START */
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.long 0x00000000 /* INITRD_SIZE */
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#ifdef CONFIG_32BIT
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.long 0x53453f00 + 32 /* "SE?" = 32 bit */
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#else
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.long 0x53453f00 + 29 /* "SE?" = 29 bit */
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#endif
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1:
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.skip PAGE_SIZE - empty_zero_page - 1b
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__HEAD
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/*
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* Condition at the entry of _stext:
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*
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* BSC has already been initialized.
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* INTC may or may not be initialized.
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* VBR may or may not be initialized.
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* MMU may or may not be initialized.
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* Cache may or may not be initialized.
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* Hardware (including on-chip modules) may or may not be initialized.
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*
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*/
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ENTRY(_stext)
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! Initialize Status Register
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mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF
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ldc r0, sr
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! Initialize global interrupt mask
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#ifdef CONFIG_CPU_HAS_SR_RB
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mov #0, r0
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ldc r0, r6_bank
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#endif
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/*
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* Prefetch if possible to reduce cache miss penalty.
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*
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* We do this early on for SH-4A as a micro-optimization,
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* as later on we will have speculative execution enabled
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* and this will become less of an issue.
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*/
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PREFI(5f, r0)
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PREFI(6f, r0)
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!
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mov.l 2f, r0
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mov r0, r15 ! Set initial r15 (stack pointer)
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#ifdef CONFIG_CPU_HAS_SR_RB
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mov.l 7f, r0
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ldc r0, r7_bank ! ... and initial thread_info
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#endif
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#if defined(CONFIG_PMB) && !defined(CONFIG_PMB_LEGACY)
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/*
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* Reconfigure the initial PMB mappings setup by the hardware.
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*
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* When we boot in 32-bit MMU mode there are 2 PMB entries already
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* setup for us.
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*
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* Entry VPN PPN V SZ C UB WT
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* ---------------------------------------------------------------
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* 0 0x80000000 0x00000000 1 512MB 1 0 1
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* 1 0xA0000000 0x00000000 1 512MB 0 0 0
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*
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* But we reprogram them here because we want complete control over
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* our address space and the initial mappings may not map PAGE_OFFSET
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* to __MEMORY_START (or even map all of our RAM).
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*
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* Once we've setup cached and uncached mappings for all of RAM we
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* clear the rest of the PMB entries.
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*
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* This clearing also deals with the fact that PMB entries can persist
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* across reboots. The PMB could have been left in any state when the
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* reboot occurred, so to be safe we clear all entries and start with
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* with a clean slate.
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*/
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mov.l .LMMUCR, r1 /* Flush the TLB */
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mov.l @r1, r0
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or #MMUCR_TI, r0
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mov.l r0, @r1
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mov.l .LMEMORY_SIZE, r5
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mov r5, r7
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mov #PMB_E_SHIFT, r0
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mov #0x1, r4
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shld r0, r4
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mov.l .LFIRST_DATA_ENTRY, r0
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mov.l .LPMB_DATA, r1
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mov.l .LFIRST_ADDR_ENTRY, r2
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mov.l .LPMB_ADDR, r3
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mov #0, r10
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/*
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* r0 = PMB_DATA data field
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* r1 = PMB_DATA address field
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* r2 = PMB_ADDR data field
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* r3 = PMB_ADDR address field
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* r4 = PMB_E_SHIFT
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* r5 = remaining amount of RAM to map
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* r6 = PMB mapping size we're trying to use
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* r7 = cached_to_uncached
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* r8 = scratch register
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* r9 = scratch register
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* r10 = number of PMB entries we've setup
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*/
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.L512:
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mov #(512 >> 4), r6
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shll16 r6
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shll8 r6
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cmp/hi r5, r6
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bt .L128
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mov #(PMB_SZ_512M >> 2), r9
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shll2 r9
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/*
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* Cached mapping
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*/
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mov #PMB_C, r8
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or r0, r8
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or r9, r8
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mov.l r8, @r1
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mov.l r2, @r3
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add r4, r1 /* Increment to the next PMB_DATA entry */
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add r4, r3 /* Increment to the next PMB_ADDR entry */
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add #1, r10 /* Increment number of PMB entries */
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/*
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* Uncached mapping
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*/
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mov #(PMB_UB >> 8), r8
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shll8 r8
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or r0, r8
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or r9, r8
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mov.l r8, @r1
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mov r2, r8
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add r7, r8
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mov.l r8, @r3
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add r4, r1 /* Increment to the next PMB_DATA entry */
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add r4, r3 /* Increment to the next PMB_ADDR entry */
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add #1, r10 /* Increment number of PMB entries */
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sub r6, r5
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add r6, r0
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add r6, r2
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bra .L512
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.L128:
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mov #(128 >> 4), r6
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shll16 r6
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shll8 r6
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cmp/hi r5, r6
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bt .L64
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mov #(PMB_SZ_128M >> 2), r9
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shll2 r9
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/*
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* Cached mapping
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*/
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mov #PMB_C, r8
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or r0, r8
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or r9, r8
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mov.l r8, @r1
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mov.l r2, @r3
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add r4, r1 /* Increment to the next PMB_DATA entry */
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add r4, r3 /* Increment to the next PMB_ADDR entry */
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add #1, r10 /* Increment number of PMB entries */
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/*
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* Uncached mapping
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*/
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mov #(PMB_UB >> 8), r8
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shll8 r8
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or r0, r8
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or r9, r8
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mov.l r8, @r1
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mov r2, r8
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add r7, r8
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mov.l r8, @r3
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add r4, r1 /* Increment to the next PMB_DATA entry */
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add r4, r3 /* Increment to the next PMB_ADDR entry */
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add #1, r10 /* Increment number of PMB entries */
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sub r6, r5
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add r6, r0
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add r6, r2
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bra .L128
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.L64:
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mov #(64 >> 4), r6
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shll16 r6
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shll8 r6
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cmp/hi r5, r6
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bt .Ldone
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mov #(PMB_SZ_64M >> 2), r9
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shll2 r9
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/*
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* Cached mapping
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*/
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mov #PMB_C, r8
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or r0, r8
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or r9, r8
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mov.l r8, @r1
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mov.l r2, @r3
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add r4, r1 /* Increment to the next PMB_DATA entry */
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add r4, r3 /* Increment to the next PMB_ADDR entry */
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add #1, r10 /* Increment number of PMB entries */
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/*
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* Uncached mapping
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*/
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mov #(PMB_UB >> 8), r8
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shll8 r8
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or r0, r8
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or r9, r8
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mov.l r8, @r1
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mov r2, r8
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add r7, r8
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mov.l r8, @r3
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add r4, r1 /* Increment to the next PMB_DATA entry */
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add r4, r3 /* Increment to the next PMB_ADDR entry */
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add #1, r10 /* Increment number of PMB entries */
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sub r6, r5
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add r6, r0
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add r6, r2
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bra .L64
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.Ldone:
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/* Update cached_to_uncached */
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mov.l .Lcached_to_uncached, r0
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mov.l r7, @r0
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/*
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* Clear the remaining PMB entries.
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*
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* r3 = entry to begin clearing from
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* r10 = number of entries we've setup so far
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*/
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mov #0, r1
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mov #PMB_ENTRY_MAX, r0
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.Lagain:
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mov.l r1, @r3 /* Clear PMB_ADDR entry */
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add #1, r10 /* Increment the loop counter */
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cmp/eq r0, r10
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bf/s .Lagain
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add r4, r3 /* Increment to the next PMB_ADDR entry */
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mov.l 6f, r0
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icbi @r0
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#endif /* !CONFIG_PMB_LEGACY */
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#ifndef CONFIG_SH_NO_BSS_INIT
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/*
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* Don't clear BSS if running on slow platforms such as an RTL simulation,
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* remote memory via SHdebug link, etc. For these the memory can be guaranteed
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* to be all zero on boot anyway.
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*/
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! Clear BSS area
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#ifdef CONFIG_SMP
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mov.l 3f, r0
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cmp/eq #0, r0 ! skip clear if set to zero
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bt 10f
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#endif
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mov.l 3f, r1
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add #4, r1
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mov.l 4f, r2
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mov #0, r0
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9: cmp/hs r2, r1
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bf/s 9b ! while (r1 < r2)
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mov.l r0,@-r2
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10:
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#endif
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! Additional CPU initialization
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mov.l 6f, r0
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jsr @r0
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nop
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SYNCO() ! Wait for pending instructions..
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! Start kernel
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mov.l 5f, r0
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jmp @r0
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nop
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.balign 4
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#if defined(CONFIG_CPU_SH2)
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1: .long 0x000000F0 ! IMASK=0xF
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#else
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1: .long 0x400080F0 ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF
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#endif
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ENTRY(stack_start)
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2: .long init_thread_union+THREAD_SIZE
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3: .long __bss_start
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4: .long _end
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5: .long start_kernel
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6: .long sh_cpu_init
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7: .long init_thread_union
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#if defined(CONFIG_PMB) && !defined(CONFIG_PMB_LEGACY)
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.LPMB_ADDR: .long PMB_ADDR
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.LPMB_DATA: .long PMB_DATA
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.LFIRST_ADDR_ENTRY: .long PAGE_OFFSET | PMB_V
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.LFIRST_DATA_ENTRY: .long __MEMORY_START | PMB_V
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.LMMUCR: .long MMUCR
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.Lcached_to_uncached: .long cached_to_uncached
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.LMEMORY_SIZE: .long __MEMORY_SIZE
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#endif
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