![Paul Mackerras](/assets/img/avatar_default.png)
Some POWER5+ machines can do 64k hardware pages for normal memory but not for cache-inhibited pages. This patch lets us use 64k hardware pages for most user processes on such machines (assuming the kernel has been configured with CONFIG_PPC_64K_PAGES=y). User processes start out using 64k pages and get switched to 4k pages if they use any non-cacheable mappings. With this, we use 64k pages for the vmalloc region and 4k pages for the imalloc region. If anything creates a non-cacheable mapping in the vmalloc region, the vmalloc region will get switched to 4k pages. I don't know of any driver other than the DRM that would do this, though, and these machines don't have AGP. When a region gets switched from 64k pages to 4k pages, we do not have to clear out all the 64k HPTEs from the hash table immediately. We use the _PAGE_COMBO bit in the Linux PTE to indicate whether the page was hashed in as a 64k page or a set of 4k pages. If hash_page is trying to insert a 4k page for a Linux PTE and it sees that it has already been inserted as a 64k page, it first invalidates the 64k HPTE before inserting the 4k HPTE. The hash invalidation routines also use the _PAGE_COMBO bit, to determine whether to look for a 64k HPTE or a set of 4k HPTEs to remove. With those two changes, we can tolerate a mix of 4k and 64k HPTEs in the hash table, and they will all get removed when the address space is torn down. Signed-off-by: Paul Mackerras <paulus@samba.org>
217 lines
5.5 KiB
C
217 lines
5.5 KiB
C
/*
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* This file contains the routines for flushing entries from the
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* TLB and MMU hash table.
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*
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* Derived from arch/ppc64/mm/init.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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* Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* Dave Engebretsen <engebret@us.ibm.com>
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* Rework for PPC64 port.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/percpu.h>
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#include <linux/hardirq.h>
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#include <asm/tlb.h>
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#include <asm/bug.h>
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DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
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/* This is declared as we are using the more or less generic
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* include/asm-powerpc/tlb.h file -- tgall
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*/
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DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
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DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
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unsigned long pte_freelist_forced_free;
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struct pte_freelist_batch
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{
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struct rcu_head rcu;
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unsigned int index;
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pgtable_free_t tables[0];
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};
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DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
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unsigned long pte_freelist_forced_free;
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#define PTE_FREELIST_SIZE \
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((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \
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/ sizeof(pgtable_free_t))
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#ifdef CONFIG_SMP
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static void pte_free_smp_sync(void *arg)
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{
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/* Do nothing, just ensure we sync with all CPUs */
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}
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#endif
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/* This is only called when we are critically out of memory
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* (and fail to get a page in pte_free_tlb).
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*/
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static void pgtable_free_now(pgtable_free_t pgf)
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{
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pte_freelist_forced_free++;
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smp_call_function(pte_free_smp_sync, NULL, 0, 1);
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pgtable_free(pgf);
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}
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static void pte_free_rcu_callback(struct rcu_head *head)
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{
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struct pte_freelist_batch *batch =
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container_of(head, struct pte_freelist_batch, rcu);
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unsigned int i;
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for (i = 0; i < batch->index; i++)
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pgtable_free(batch->tables[i]);
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free_page((unsigned long)batch);
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}
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static void pte_free_submit(struct pte_freelist_batch *batch)
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{
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INIT_RCU_HEAD(&batch->rcu);
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call_rcu(&batch->rcu, pte_free_rcu_callback);
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}
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void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf)
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{
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/* This is safe since tlb_gather_mmu has disabled preemption */
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cpumask_t local_cpumask = cpumask_of_cpu(smp_processor_id());
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struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
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if (atomic_read(&tlb->mm->mm_users) < 2 ||
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cpus_equal(tlb->mm->cpu_vm_mask, local_cpumask)) {
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pgtable_free(pgf);
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return;
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}
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if (*batchp == NULL) {
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*batchp = (struct pte_freelist_batch *)__get_free_page(GFP_ATOMIC);
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if (*batchp == NULL) {
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pgtable_free_now(pgf);
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return;
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}
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(*batchp)->index = 0;
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}
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(*batchp)->tables[(*batchp)->index++] = pgf;
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if ((*batchp)->index == PTE_FREELIST_SIZE) {
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pte_free_submit(*batchp);
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*batchp = NULL;
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}
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}
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/*
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* Update the MMU hash table to correspond with a change to
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* a Linux PTE. If wrprot is true, it is permissible to
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* change the existing HPTE to read-only rather than removing it
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* (if we remove it we should clear the _PTE_HPTEFLAGS bits).
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*/
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void hpte_update(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, unsigned long pte, int huge)
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{
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struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
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unsigned long vsid;
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unsigned int psize;
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int i;
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i = batch->index;
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/* We mask the address for the base page size. Huge pages will
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* have applied their own masking already
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*/
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addr &= PAGE_MASK;
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/* Get page size (maybe move back to caller) */
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if (huge) {
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#ifdef CONFIG_HUGETLB_PAGE
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psize = mmu_huge_psize;
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#else
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BUG();
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#endif
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} else
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psize = pte_pagesize_index(pte);
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/*
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* This can happen when we are in the middle of a TLB batch and
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* we encounter memory pressure (eg copy_page_range when it tries
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* to allocate a new pte). If we have to reclaim memory and end
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* up scanning and resetting referenced bits then our batch context
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* will change mid stream.
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*
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* We also need to ensure only one page size is present in a given
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* batch
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*/
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if (i != 0 && (mm != batch->mm || batch->psize != psize)) {
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flush_tlb_pending();
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i = 0;
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}
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if (i == 0) {
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batch->mm = mm;
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batch->psize = psize;
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}
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if (!is_kernel_addr(addr)) {
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vsid = get_vsid(mm->context.id, addr);
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WARN_ON(vsid == 0);
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} else
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vsid = get_kernel_vsid(addr);
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batch->vaddr[i] = (vsid << 28 ) | (addr & 0x0fffffff);
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batch->pte[i] = __real_pte(__pte(pte), ptep);
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batch->index = ++i;
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if (i >= PPC64_TLB_BATCH_NR)
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flush_tlb_pending();
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}
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void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
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{
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int i;
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int cpu;
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cpumask_t tmp;
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int local = 0;
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BUG_ON(in_interrupt());
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cpu = get_cpu();
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i = batch->index;
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tmp = cpumask_of_cpu(cpu);
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if (cpus_equal(batch->mm->cpu_vm_mask, tmp))
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local = 1;
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if (i == 1)
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flush_hash_page(batch->vaddr[0], batch->pte[0],
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batch->psize, local);
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else
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flush_hash_range(i, local);
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batch->index = 0;
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put_cpu();
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}
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void pte_free_finish(void)
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{
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/* This is safe since tlb_gather_mmu has disabled preemption */
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struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
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if (*batchp == NULL)
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return;
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pte_free_submit(*batchp);
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*batchp = NULL;
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}
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