543 lines
16 KiB
C
543 lines
16 KiB
C
/*
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* Copyright (C) 2007 Ben Skeggs.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_ramht.h"
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#include "nouveau_util.h"
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#define NV04_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV04_RAMFC__SIZE))
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#define NV04_RAMFC__SIZE 32
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#define NV04_RAMFC_DMA_PUT 0x00
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#define NV04_RAMFC_DMA_GET 0x04
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#define NV04_RAMFC_DMA_INSTANCE 0x08
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#define NV04_RAMFC_DMA_STATE 0x0C
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#define NV04_RAMFC_DMA_FETCH 0x10
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#define NV04_RAMFC_ENGINE 0x14
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#define NV04_RAMFC_PULL1_ENGINE 0x18
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#define RAMFC_WR(offset, val) nv_wo32(chan->ramfc, NV04_RAMFC_##offset, (val))
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#define RAMFC_RD(offset) nv_ro32(chan->ramfc, NV04_RAMFC_##offset)
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void
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nv04_fifo_disable(struct drm_device *dev)
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{
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uint32_t tmp;
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tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH);
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, tmp & ~1);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 0);
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tmp = nv_rd32(dev, NV03_PFIFO_CACHE1_PULL1);
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nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, tmp & ~1);
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}
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void
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nv04_fifo_enable(struct drm_device *dev)
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{
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
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nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
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}
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bool
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nv04_fifo_reassign(struct drm_device *dev, bool enable)
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{
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uint32_t reassign = nv_rd32(dev, NV03_PFIFO_CACHES);
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nv_wr32(dev, NV03_PFIFO_CACHES, enable ? 1 : 0);
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return (reassign == 1);
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}
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bool
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nv04_fifo_cache_pull(struct drm_device *dev, bool enable)
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{
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int pull = nv_mask(dev, NV04_PFIFO_CACHE1_PULL0, 1, enable);
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if (!enable) {
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/* In some cases the PFIFO puller may be left in an
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* inconsistent state if you try to stop it when it's
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* busy translating handles. Sometimes you get a
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* PFIFO_CACHE_ERROR, sometimes it just fails silently
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* sending incorrect instance offsets to PGRAPH after
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* it's started up again. To avoid the latter we
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* invalidate the most recently calculated instance.
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*/
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if (!nv_wait(dev, NV04_PFIFO_CACHE1_PULL0,
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NV04_PFIFO_CACHE1_PULL0_HASH_BUSY, 0))
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NV_ERROR(dev, "Timeout idling the PFIFO puller.\n");
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if (nv_rd32(dev, NV04_PFIFO_CACHE1_PULL0) &
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NV04_PFIFO_CACHE1_PULL0_HASH_FAILED)
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nv_wr32(dev, NV03_PFIFO_INTR_0,
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NV_PFIFO_INTR_CACHE_ERROR);
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nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
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}
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return pull & 1;
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}
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int
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nv04_fifo_channel_id(struct drm_device *dev)
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{
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return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
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NV03_PFIFO_CACHE1_PUSH1_CHID_MASK;
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}
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#ifdef __BIG_ENDIAN
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#define DMA_FETCH_ENDIANNESS NV_PFIFO_CACHE1_BIG_ENDIAN
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#else
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#define DMA_FETCH_ENDIANNESS 0
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#endif
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int
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nv04_fifo_create_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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unsigned long flags;
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int ret;
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ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), ~0,
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NV04_RAMFC__SIZE,
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NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE,
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&chan->ramfc);
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if (ret)
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return ret;
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chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
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NV03_USER(chan->id), PAGE_SIZE);
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if (!chan->user)
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return -ENOMEM;
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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/* Setup initial state */
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RAMFC_WR(DMA_PUT, chan->pushbuf_base);
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RAMFC_WR(DMA_GET, chan->pushbuf_base);
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RAMFC_WR(DMA_INSTANCE, chan->pushbuf->pinst >> 4);
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RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
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NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
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NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
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DMA_FETCH_ENDIANNESS));
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/* enable the fifo dma operation */
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nv_wr32(dev, NV04_PFIFO_MODE,
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nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id));
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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return 0;
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}
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void
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nv04_fifo_destroy_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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unsigned long flags;
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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pfifo->reassign(dev, false);
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/* Unload the context if it's the currently active one */
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if (pfifo->channel_id(dev) == chan->id) {
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pfifo->disable(dev);
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pfifo->unload_context(dev);
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pfifo->enable(dev);
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}
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/* Keep it from being rescheduled */
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nv_mask(dev, NV04_PFIFO_MODE, 1 << chan->id, 0);
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pfifo->reassign(dev, true);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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/* Free the channel resources */
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if (chan->user) {
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iounmap(chan->user);
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chan->user = NULL;
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}
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nouveau_gpuobj_ref(NULL, &chan->ramfc);
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}
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static void
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nv04_fifo_do_load_context(struct drm_device *dev, int chid)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t fc = NV04_RAMFC(chid), tmp;
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
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tmp = nv_ri32(dev, fc + 8);
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 12));
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, nv_ri32(dev, fc + 16));
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nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 20));
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nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 24));
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nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
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}
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int
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nv04_fifo_load_context(struct nouveau_channel *chan)
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{
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uint32_t tmp;
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nv_wr32(chan->dev, NV03_PFIFO_CACHE1_PUSH1,
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NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
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nv04_fifo_do_load_context(chan->dev, chan->id);
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nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
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/* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
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tmp = nv_rd32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
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nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
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return 0;
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}
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int
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nv04_fifo_unload_context(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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struct nouveau_channel *chan = NULL;
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uint32_t tmp;
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int chid;
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chid = pfifo->channel_id(dev);
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if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
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return 0;
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chan = dev_priv->channels.ptr[chid];
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if (!chan) {
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NV_ERROR(dev, "Inactive channel on PFIFO: %d\n", chid);
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return -EINVAL;
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}
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RAMFC_WR(DMA_PUT, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
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RAMFC_WR(DMA_GET, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
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tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16;
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tmp |= nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE);
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RAMFC_WR(DMA_INSTANCE, tmp);
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RAMFC_WR(DMA_STATE, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
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RAMFC_WR(DMA_FETCH, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH));
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RAMFC_WR(ENGINE, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
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RAMFC_WR(PULL1_ENGINE, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
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nv04_fifo_do_load_context(dev, pfifo->channels - 1);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
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return 0;
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}
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static void
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nv04_fifo_init_reset(struct drm_device *dev)
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{
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nv_wr32(dev, NV03_PMC_ENABLE,
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nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
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nv_wr32(dev, NV03_PMC_ENABLE,
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nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PFIFO);
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nv_wr32(dev, 0x003224, 0x000f0078);
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nv_wr32(dev, 0x002044, 0x0101ffff);
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nv_wr32(dev, 0x002040, 0x000000ff);
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nv_wr32(dev, 0x002500, 0x00000000);
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nv_wr32(dev, 0x003000, 0x00000000);
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nv_wr32(dev, 0x003050, 0x00000000);
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nv_wr32(dev, 0x003200, 0x00000000);
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nv_wr32(dev, 0x003250, 0x00000000);
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nv_wr32(dev, 0x003220, 0x00000000);
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nv_wr32(dev, 0x003250, 0x00000000);
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nv_wr32(dev, 0x003270, 0x00000000);
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nv_wr32(dev, 0x003210, 0x00000000);
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}
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static void
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nv04_fifo_init_ramxx(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
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((dev_priv->ramht->bits - 9) << 16) |
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(dev_priv->ramht->gpuobj->pinst >> 8));
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nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8);
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nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc->pinst >> 8);
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}
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static void
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nv04_fifo_init_intr(struct drm_device *dev)
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{
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nouveau_irq_register(dev, 8, nv04_fifo_isr);
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nv_wr32(dev, 0x002100, 0xffffffff);
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nv_wr32(dev, 0x002140, 0xffffffff);
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}
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int
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nv04_fifo_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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int i;
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nv04_fifo_init_reset(dev);
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nv04_fifo_init_ramxx(dev);
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nv04_fifo_do_load_context(dev, pfifo->channels - 1);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
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nv04_fifo_init_intr(dev);
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pfifo->enable(dev);
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pfifo->reassign(dev, true);
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for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
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if (dev_priv->channels.ptr[i]) {
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uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
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nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i));
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}
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}
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return 0;
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}
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void
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nv04_fifo_fini(struct drm_device *dev)
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{
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nv_wr32(dev, 0x2140, 0x00000000);
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nouveau_irq_unregister(dev, 8);
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}
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static bool
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nouveau_fifo_swmthd(struct drm_device *dev, u32 chid, u32 addr, u32 data)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_channel *chan = NULL;
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struct nouveau_gpuobj *obj;
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unsigned long flags;
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const int subc = (addr >> 13) & 0x7;
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const int mthd = addr & 0x1ffc;
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bool handled = false;
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u32 engine;
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spin_lock_irqsave(&dev_priv->channels.lock, flags);
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if (likely(chid >= 0 && chid < dev_priv->engine.fifo.channels))
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chan = dev_priv->channels.ptr[chid];
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if (unlikely(!chan))
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goto out;
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switch (mthd) {
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case 0x0000: /* bind object to subchannel */
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obj = nouveau_ramht_find(chan, data);
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if (unlikely(!obj || obj->engine != NVOBJ_ENGINE_SW))
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break;
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chan->sw_subchannel[subc] = obj->class;
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engine = 0x0000000f << (subc * 4);
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nv_mask(dev, NV04_PFIFO_CACHE1_ENGINE, engine, 0x00000000);
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handled = true;
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break;
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default:
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engine = nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE);
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if (unlikely(((engine >> (subc * 4)) & 0xf) != 0))
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break;
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if (!nouveau_gpuobj_mthd_call(chan, chan->sw_subchannel[subc],
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mthd, data))
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handled = true;
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break;
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}
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out:
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spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
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return handled;
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}
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static const char *nv_dma_state_err(u32 state)
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{
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static const char * const desc[] = {
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"NONE", "CALL_SUBR_ACTIVE", "INVALID_MTHD", "RET_SUBR_INACTIVE",
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"INVALID_CMD", "IB_EMPTY"/* NV50+ */, "MEM_FAULT", "UNK"
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};
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return desc[(state >> 29) & 0x7];
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}
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void
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nv04_fifo_isr(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_engine *engine = &dev_priv->engine;
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uint32_t status, reassign;
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int cnt = 0;
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reassign = nv_rd32(dev, NV03_PFIFO_CACHES) & 1;
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while ((status = nv_rd32(dev, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {
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uint32_t chid, get;
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nv_wr32(dev, NV03_PFIFO_CACHES, 0);
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chid = engine->fifo.channel_id(dev);
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get = nv_rd32(dev, NV03_PFIFO_CACHE1_GET);
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if (status & NV_PFIFO_INTR_CACHE_ERROR) {
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uint32_t mthd, data;
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int ptr;
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/* NV_PFIFO_CACHE1_GET actually goes to 0xffc before
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* wrapping on my G80 chips, but CACHE1 isn't big
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* enough for this much data.. Tests show that it
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* wraps around to the start at GET=0x800.. No clue
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* as to why..
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*/
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ptr = (get & 0x7ff) >> 2;
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if (dev_priv->card_type < NV_40) {
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mthd = nv_rd32(dev,
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NV04_PFIFO_CACHE1_METHOD(ptr));
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data = nv_rd32(dev,
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NV04_PFIFO_CACHE1_DATA(ptr));
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} else {
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mthd = nv_rd32(dev,
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NV40_PFIFO_CACHE1_METHOD(ptr));
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data = nv_rd32(dev,
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NV40_PFIFO_CACHE1_DATA(ptr));
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}
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if (!nouveau_fifo_swmthd(dev, chid, mthd, data)) {
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NV_INFO(dev, "PFIFO_CACHE_ERROR - Ch %d/%d "
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"Mthd 0x%04x Data 0x%08x\n",
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chid, (mthd >> 13) & 7, mthd & 0x1ffc,
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data);
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}
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
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nv_wr32(dev, NV03_PFIFO_INTR_0,
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NV_PFIFO_INTR_CACHE_ERROR);
|
|
|
|
nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
|
|
nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) & ~1);
|
|
nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
|
|
nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
|
|
nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) | 1);
|
|
nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
|
|
|
|
nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH,
|
|
nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
|
|
nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
|
|
|
|
status &= ~NV_PFIFO_INTR_CACHE_ERROR;
|
|
}
|
|
|
|
if (status & NV_PFIFO_INTR_DMA_PUSHER) {
|
|
u32 dma_get = nv_rd32(dev, 0x003244);
|
|
u32 dma_put = nv_rd32(dev, 0x003240);
|
|
u32 push = nv_rd32(dev, 0x003220);
|
|
u32 state = nv_rd32(dev, 0x003228);
|
|
|
|
if (dev_priv->card_type == NV_50) {
|
|
u32 ho_get = nv_rd32(dev, 0x003328);
|
|
u32 ho_put = nv_rd32(dev, 0x003320);
|
|
u32 ib_get = nv_rd32(dev, 0x003334);
|
|
u32 ib_put = nv_rd32(dev, 0x003330);
|
|
|
|
if (nouveau_ratelimit())
|
|
NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%02x%08x "
|
|
"Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x "
|
|
"State 0x%08x (err: %s) Push 0x%08x\n",
|
|
chid, ho_get, dma_get, ho_put,
|
|
dma_put, ib_get, ib_put, state,
|
|
nv_dma_state_err(state),
|
|
push);
|
|
|
|
/* METHOD_COUNT, in DMA_STATE on earlier chipsets */
|
|
nv_wr32(dev, 0x003364, 0x00000000);
|
|
if (dma_get != dma_put || ho_get != ho_put) {
|
|
nv_wr32(dev, 0x003244, dma_put);
|
|
nv_wr32(dev, 0x003328, ho_put);
|
|
} else
|
|
if (ib_get != ib_put) {
|
|
nv_wr32(dev, 0x003334, ib_put);
|
|
}
|
|
} else {
|
|
NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%08x "
|
|
"Put 0x%08x State 0x%08x (err: %s) Push 0x%08x\n",
|
|
chid, dma_get, dma_put, state,
|
|
nv_dma_state_err(state), push);
|
|
|
|
if (dma_get != dma_put)
|
|
nv_wr32(dev, 0x003244, dma_put);
|
|
}
|
|
|
|
nv_wr32(dev, 0x003228, 0x00000000);
|
|
nv_wr32(dev, 0x003220, 0x00000001);
|
|
nv_wr32(dev, 0x002100, NV_PFIFO_INTR_DMA_PUSHER);
|
|
status &= ~NV_PFIFO_INTR_DMA_PUSHER;
|
|
}
|
|
|
|
if (status & NV_PFIFO_INTR_SEMAPHORE) {
|
|
uint32_t sem;
|
|
|
|
status &= ~NV_PFIFO_INTR_SEMAPHORE;
|
|
nv_wr32(dev, NV03_PFIFO_INTR_0,
|
|
NV_PFIFO_INTR_SEMAPHORE);
|
|
|
|
sem = nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE);
|
|
nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
|
|
|
|
nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
|
|
nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
|
|
}
|
|
|
|
if (dev_priv->card_type == NV_50) {
|
|
if (status & 0x00000010) {
|
|
nv50_fb_vm_trap(dev, nouveau_ratelimit());
|
|
status &= ~0x00000010;
|
|
nv_wr32(dev, 0x002100, 0x00000010);
|
|
}
|
|
}
|
|
|
|
if (status) {
|
|
if (nouveau_ratelimit())
|
|
NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n",
|
|
status, chid);
|
|
nv_wr32(dev, NV03_PFIFO_INTR_0, status);
|
|
status = 0;
|
|
}
|
|
|
|
nv_wr32(dev, NV03_PFIFO_CACHES, reassign);
|
|
}
|
|
|
|
if (status) {
|
|
NV_INFO(dev, "PFIFO still angry after %d spins, halt\n", cnt);
|
|
nv_wr32(dev, 0x2140, 0);
|
|
nv_wr32(dev, 0x140, 0);
|
|
}
|
|
|
|
nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
|
|
}
|