5d36a3321b
The patch allows Async3 clock source to be selected between PLL1 SYSCLK2 and PLL0 SYSCLK2. Having Async3 source from PLL1 SYSCLK2 allows peripherals on that domain to remain unaffected by frequency scaling on PLL0. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
111 lines
2.8 KiB
C
111 lines
2.8 KiB
C
/*
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* TI DaVinci clock definitions
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*
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* Copyright (C) 2006-2007 Texas Instruments.
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* Copyright (C) 2008-2009 Deep Root Systems, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
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#define __ARCH_ARM_DAVINCI_CLOCK_H
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#include <linux/list.h>
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#include <asm/clkdev.h>
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#define DAVINCI_PLL1_BASE 0x01c40800
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#define DAVINCI_PLL2_BASE 0x01c40c00
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#define MAX_PLL 2
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/* PLL/Reset register offsets */
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#define PLLCTL 0x100
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#define PLLCTL_PLLEN BIT(0)
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#define PLLCTL_PLLPWRDN BIT(1)
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#define PLLCTL_PLLRST BIT(3)
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#define PLLCTL_PLLDIS BIT(4)
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#define PLLCTL_PLLENSRC BIT(5)
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#define PLLCTL_CLKMODE BIT(8)
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#define PLLM 0x110
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#define PLLM_PLLM_MASK 0xff
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#define PREDIV 0x114
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#define PLLDIV1 0x118
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#define PLLDIV2 0x11c
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#define PLLDIV3 0x120
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#define POSTDIV 0x128
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#define BPDIV 0x12c
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#define PLLCMD 0x138
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#define PLLSTAT 0x13c
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#define PLLALNCTL 0x140
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#define PLLDCHANGE 0x144
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#define PLLCKEN 0x148
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#define PLLCKSTAT 0x14c
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#define PLLSYSTAT 0x150
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#define PLLDIV4 0x160
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#define PLLDIV5 0x164
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#define PLLDIV6 0x168
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#define PLLDIV7 0x16c
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#define PLLDIV8 0x170
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#define PLLDIV9 0x174
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#define PLLDIV_EN BIT(15)
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#define PLLDIV_RATIO_MASK 0x1f
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struct pll_data {
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u32 phys_base;
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void __iomem *base;
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u32 num;
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u32 flags;
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u32 input_rate;
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};
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#define PLL_HAS_PREDIV 0x01
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#define PLL_HAS_POSTDIV 0x02
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struct clk {
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struct list_head node;
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struct module *owner;
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const char *name;
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unsigned long rate;
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u8 usecount;
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u8 lpsc;
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u8 psc_ctlr;
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u32 flags;
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struct clk *parent;
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struct list_head children; /* list of children */
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struct list_head childnode; /* parent's child list node */
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struct pll_data *pll_data;
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u32 div_reg;
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unsigned long (*recalc) (struct clk *);
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int (*set_rate) (struct clk *clk, unsigned long rate);
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int (*round_rate) (struct clk *clk, unsigned long rate);
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};
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/* Clock flags: SoC-specific flags start at BIT(16) */
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#define ALWAYS_ENABLED BIT(1)
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#define CLK_PSC BIT(2)
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#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
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#define CLK_PLL BIT(4) /* PLL-derived clock */
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#define PRE_PLL BIT(5) /* source is before PLL mult/div */
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struct davinci_clk {
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struct clk_lookup lk;
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};
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#define CLK(dev, con, ck) \
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{ \
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.lk = { \
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.dev_id = dev, \
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.con_id = con, \
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.clk = ck, \
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}, \
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}
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int davinci_clk_init(struct davinci_clk *clocks);
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int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
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unsigned int mult, unsigned int postdiv);
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extern struct platform_device davinci_wdt_device;
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#endif
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