1193 lines
36 KiB
C
1193 lines
36 KiB
C
/*
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*************************************************************************
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* Ralink Tech Inc.
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* 5F., No.36, Taiyuan St., Jhubei City,
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* Hsinchu County 302,
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* Taiwan, R.O.C.
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*
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* (c) Copyright 2002-2007, Ralink Technology, Inc.
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*
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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* *
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*************************************************************************
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Module Name:
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pci_main_dev.c
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Abstract:
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Create and register network interface for PCI based chipsets in Linux platform.
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Revision History:
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Who When What
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Justin P. Mattock 11/07/2010 Fix typos in some comments
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-------- ---------- ----------------------------------------------
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*/
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#include "rt_config.h"
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#include <linux/pci.h>
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#include <linux/slab.h>
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/* Following information will be show when you run 'modinfo' */
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/* If you have a solution for a bug in current version of driver, please e-mail me. */
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/* Otherwise post to forum in ralinktech's web site(www.ralinktech.com) and let all users help you. */
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MODULE_AUTHOR("Jett Chen <jett_chen@ralinktech.com>");
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MODULE_DESCRIPTION("RT2860/RT3090 Wireless Lan Linux Driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("rt3090sta");
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/* */
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/* Function declarations */
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/* */
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static void __devexit rt2860_remove_one(struct pci_dev *pci_dev);
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static int __devinit rt2860_probe(struct pci_dev *pci_dev,
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const struct pci_device_id *ent);
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static void __exit rt2860_cleanup_module(void);
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static int __init rt2860_init_module(void);
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static void RTMPInitPCIeDevice(IN struct pci_dev *pci_dev,
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struct rt_rtmp_adapter *pAd);
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#ifdef CONFIG_PM
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static int rt2860_suspend(struct pci_dev *pci_dev, pm_message_t state);
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static int rt2860_resume(struct pci_dev *pci_dev);
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#endif /* CONFIG_PM // */
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/* */
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/* Ralink PCI device table, include all supported chipsets */
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/* */
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static struct pci_device_id rt2860_pci_tbl[] __devinitdata = {
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#ifdef RT2860
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2860_PCI_DEVICE_ID)}, /*RT28602.4G */
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2860_PCIe_DEVICE_ID)},
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2760_PCI_DEVICE_ID)},
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2790_PCIe_DEVICE_ID)},
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{PCI_DEVICE(VEN_AWT_PCI_VENDOR_ID, VEN_AWT_PCIe_DEVICE_ID)},
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{PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7708)},
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{PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7728)},
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{PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7758)},
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{PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7727)},
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{PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7738)},
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{PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7748)},
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{PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7768)},
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#endif
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#ifdef RT3090
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3090_PCIe_DEVICE_ID)},
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3091_PCIe_DEVICE_ID)},
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3092_PCIe_DEVICE_ID)},
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#endif /* RT3090 // */
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#ifdef RT3390
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3390_PCIe_DEVICE_ID)},
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3391_PCIe_DEVICE_ID)},
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{PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3392_PCIe_DEVICE_ID)},
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#endif /* RT3390 // */
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{0,} /* terminate list */
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};
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MODULE_DEVICE_TABLE(pci, rt2860_pci_tbl);
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#ifdef MODULE_VERSION
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MODULE_VERSION(STA_DRIVER_VERSION);
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#endif
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/* */
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/* Our PCI driver structure */
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/* */
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static struct pci_driver rt2860_driver = {
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name: "rt2860",
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id_table : rt2860_pci_tbl,
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probe : rt2860_probe,
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remove : __devexit_p(rt2860_remove_one),
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#ifdef CONFIG_PM
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suspend : rt2860_suspend,
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resume : rt2860_resume,
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#endif
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};
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/***************************************************************************
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*
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* PCI device initialization related procedures.
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*
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***************************************************************************/
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#ifdef CONFIG_PM
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void RT2860RejectPendingPackets(struct rt_rtmp_adapter *pAd)
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{
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/* clear PS packets */
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/* clear TxSw packets */
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}
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static int rt2860_suspend(struct pci_dev *pci_dev, pm_message_t state)
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{
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struct net_device *net_dev = pci_get_drvdata(pci_dev);
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struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)NULL;
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int retval = 0;
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DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_suspend()\n"));
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if (net_dev == NULL) {
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DBGPRINT(RT_DEBUG_ERROR, ("net_dev == NULL!\n"));
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} else {
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GET_PAD_FROM_NET_DEV(pAd, net_dev);
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/* we can not use IFF_UP because ra0 down but ra1 up */
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/* and 1 suspend/resume function for 1 module, not for each interface */
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/* so Linux will call suspend/resume function once */
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if (VIRTUAL_IF_NUM(pAd) > 0) {
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/* avoid users do suspend after interface is down */
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/* stop interface */
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netif_carrier_off(net_dev);
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netif_stop_queue(net_dev);
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/* mark device as removed from system and therefore no longer available */
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netif_device_detach(net_dev);
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/* mark halt flag */
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RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
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RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
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/* take down the device */
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rt28xx_close((struct net_device *)net_dev);
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RT_MOD_DEC_USE_COUNT();
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}
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}
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/* reference to http://vovo2000.com/type-lab/linux/kernel-api/linux-kernel-api.html */
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/* enable device to generate PME# when suspended */
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/* pci_choose_state(): Choose the power state of a PCI device to be suspended */
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retval = pci_enable_wake(pci_dev, pci_choose_state(pci_dev, state), 1);
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/* save the PCI configuration space of a device before suspending */
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pci_save_state(pci_dev);
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/* disable PCI device after use */
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pci_disable_device(pci_dev);
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retval = pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
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DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2860_suspend()\n"));
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return retval;
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}
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static int rt2860_resume(struct pci_dev *pci_dev)
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{
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struct net_device *net_dev = pci_get_drvdata(pci_dev);
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struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)NULL;
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int retval;
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/* set the power state of a PCI device */
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/* PCI has 4 power states, DO (normal) ~ D3(less power) */
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/* in include/linux/pci.h, you can find that */
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/* #define PCI_D0 ((pci_power_t __force) 0) */
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/* #define PCI_D1 ((pci_power_t __force) 1) */
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/* #define PCI_D2 ((pci_power_t __force) 2) */
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/* #define PCI_D3hot ((pci_power_t __force) 3) */
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/* #define PCI_D3cold ((pci_power_t __force) 4) */
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/* #define PCI_UNKNOWN ((pci_power_t __force) 5) */
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/* #define PCI_POWER_ERROR ((pci_power_t __force) -1) */
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retval = pci_set_power_state(pci_dev, PCI_D0);
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/* restore the saved state of a PCI device */
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pci_restore_state(pci_dev);
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/* initialize device before it's used by a driver */
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if (pci_enable_device(pci_dev)) {
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printk(KERN_ERR "rt2860: pci enable fail!\n");
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return 0;
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}
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DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_resume()\n"));
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if (net_dev == NULL)
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DBGPRINT(RT_DEBUG_ERROR, ("net_dev == NULL!\n"));
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else
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GET_PAD_FROM_NET_DEV(pAd, net_dev);
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if (pAd != NULL) {
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/* we can not use IFF_UP because ra0 down but ra1 up */
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/* and 1 suspend/resume function for 1 module, not for each interface */
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/* so Linux will call suspend/resume function once */
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if (VIRTUAL_IF_NUM(pAd) > 0) {
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/* mark device as attached from system and restart if needed */
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netif_device_attach(net_dev);
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if (rt28xx_open((struct net_device *)net_dev) != 0) {
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/* open fail */
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DBGPRINT(RT_DEBUG_TRACE,
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("<=== rt2860_resume()\n"));
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return 0;
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}
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/* increase MODULE use count */
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RT_MOD_INC_USE_COUNT();
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RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
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RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
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netif_start_queue(net_dev);
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netif_carrier_on(net_dev);
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netif_wake_queue(net_dev);
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}
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}
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DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2860_resume()\n"));
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return 0;
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}
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#endif /* CONFIG_PM // */
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static int __init rt2860_init_module(void)
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{
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return pci_register_driver(&rt2860_driver);
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}
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/* */
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/* Driver module unload function */
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/* */
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static void __exit rt2860_cleanup_module(void)
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{
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pci_unregister_driver(&rt2860_driver);
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}
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module_init(rt2860_init_module);
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module_exit(rt2860_cleanup_module);
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/* */
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/* PCI device probe & initialization function */
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/* */
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static int __devinit rt2860_probe(IN struct pci_dev *pci_dev,
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IN const struct pci_device_id *pci_id)
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{
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struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)NULL;
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struct net_device *net_dev;
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void *handle;
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char *print_name;
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unsigned long csr_addr;
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int rv = 0;
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struct rt_rtmp_os_netdev_op_hook netDevHook;
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DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_probe\n"));
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/*PCIDevInit============================================== */
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/* wake up and enable device */
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rv = pci_enable_device(pci_dev);
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if (rv != 0) {
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DBGPRINT(RT_DEBUG_ERROR,
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("Enable PCI device failed, errno=%d!\n", rv));
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return rv;
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}
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print_name = (char *)pci_name(pci_dev);
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rv = pci_request_regions(pci_dev, print_name);
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if (rv != 0) {
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DBGPRINT(RT_DEBUG_ERROR,
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("Request PCI resource failed, errno=%d!\n", rv));
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goto err_out;
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}
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/* map physical address to virtual address for accessing register */
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csr_addr =
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(unsigned long)ioremap(pci_resource_start(pci_dev, 0),
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pci_resource_len(pci_dev, 0));
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if (!csr_addr) {
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DBGPRINT(RT_DEBUG_ERROR,
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("ioremap failed for device %s, region 0x%lX @ 0x%lX\n",
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print_name, (unsigned long)pci_resource_len(pci_dev, 0),
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(unsigned long)pci_resource_start(pci_dev, 0)));
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goto err_out_free_res;
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} else {
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DBGPRINT(RT_DEBUG_TRACE,
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("%s: at 0x%lx, VA 0x%lx, IRQ %d. \n", print_name,
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(unsigned long)pci_resource_start(pci_dev, 0),
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(unsigned long)csr_addr, pci_dev->irq));
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}
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/* Set DMA master */
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pci_set_master(pci_dev);
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/*RtmpDevInit============================================== */
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/* Allocate struct rt_rtmp_adapter adapter structure */
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handle = kmalloc(sizeof(struct os_cookie), GFP_KERNEL);
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if (handle == NULL) {
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DBGPRINT(RT_DEBUG_ERROR,
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("%s(): Allocate memory for os handle failed!\n",
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__func__));
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goto err_out_iounmap;
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}
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((struct os_cookie *)handle)->pci_dev = pci_dev;
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rv = RTMPAllocAdapterBlock(handle, &pAd); /*shiang: we may need the pci_dev for allocate structure of "struct rt_rtmp_adapter" */
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if (rv != NDIS_STATUS_SUCCESS)
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goto err_out_iounmap;
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/* Here are the struct rt_rtmp_adapter structure with pci-bus specific parameters. */
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pAd->CSRBaseAddress = (u8 *)csr_addr;
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DBGPRINT(RT_DEBUG_ERROR,
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("pAd->CSRBaseAddress =0x%lx, csr_addr=0x%lx!\n",
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(unsigned long)pAd->CSRBaseAddress, csr_addr));
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RtmpRaDevCtrlInit(pAd, RTMP_DEV_INF_PCI);
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/*NetDevInit============================================== */
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net_dev = RtmpPhyNetDevInit(pAd, &netDevHook);
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if (net_dev == NULL)
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goto err_out_free_radev;
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/* Here are the net_device structure with pci-bus specific parameters. */
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net_dev->irq = pci_dev->irq; /* Interrupt IRQ number */
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net_dev->base_addr = csr_addr; /* Save CSR virtual address and irq to device structure */
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pci_set_drvdata(pci_dev, net_dev); /* Set driver data */
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/* for supporting Network Manager */
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/* Set the sysfs physical device reference for the network logical device
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* if set prior to registration will cause a symlink during initialization.
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*/
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SET_NETDEV_DEV(net_dev, &(pci_dev->dev));
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/*All done, it's time to register the net device to linux kernel. */
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/* Register this device */
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rv = RtmpOSNetDevAttach(net_dev, &netDevHook);
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if (rv)
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goto err_out_free_netdev;
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pAd->StaCfg.OriDevType = net_dev->type;
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RTMPInitPCIeDevice(pci_dev, pAd);
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DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2860_probe\n"));
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return 0; /* probe ok */
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/* --------------------------- ERROR HANDLE --------------------------- */
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err_out_free_netdev:
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RtmpOSNetDevFree(net_dev);
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err_out_free_radev:
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/* free struct rt_rtmp_adapter strcuture and os_cookie */
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RTMPFreeAdapter(pAd);
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err_out_iounmap:
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iounmap((void *)(csr_addr));
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release_mem_region(pci_resource_start(pci_dev, 0),
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pci_resource_len(pci_dev, 0));
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err_out_free_res:
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pci_release_regions(pci_dev);
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err_out:
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pci_disable_device(pci_dev);
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DBGPRINT(RT_DEBUG_ERROR,
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("<=== rt2860_probe failed with rv = %d!\n", rv));
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return -ENODEV; /* probe fail */
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}
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static void __devexit rt2860_remove_one(IN struct pci_dev *pci_dev)
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{
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struct net_device *net_dev = pci_get_drvdata(pci_dev);
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struct rt_rtmp_adapter *pAd = NULL;
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unsigned long csr_addr = net_dev->base_addr; /* pAd->CSRBaseAddress; */
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GET_PAD_FROM_NET_DEV(pAd, net_dev);
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DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_remove_one\n"));
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if (pAd != NULL) {
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/* Unregister/Free all allocated net_device. */
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RtmpPhyNetDevExit(pAd, net_dev);
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/* Unmap CSR base address */
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iounmap((char *)(csr_addr));
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/* release memory region */
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release_mem_region(pci_resource_start(pci_dev, 0),
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pci_resource_len(pci_dev, 0));
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/* Free struct rt_rtmp_adapter related structures. */
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RtmpRaDevCtrlExit(pAd);
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} else {
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/* Unregister network device */
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RtmpOSNetDevDetach(net_dev);
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/* Unmap CSR base address */
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iounmap((char *)(net_dev->base_addr));
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/* release memory region */
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release_mem_region(pci_resource_start(pci_dev, 0),
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pci_resource_len(pci_dev, 0));
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}
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/* Free the root net_device */
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RtmpOSNetDevFree(net_dev);
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}
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/*
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========================================================================
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Routine Description:
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Check the chipset vendor/product ID.
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Arguments:
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_dev_p Point to the PCI or USB device
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Return Value:
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TRUE Check ok
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FALSE Check fail
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Note:
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========================================================================
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*/
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BOOLEAN RT28XXChipsetCheck(IN void *_dev_p)
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{
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/* always TRUE */
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return TRUE;
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}
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|
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/***************************************************************************
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|
*
|
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* PCIe device initialization related procedures.
|
|
*
|
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***************************************************************************/
|
|
static void RTMPInitPCIeDevice(struct pci_dev *pci_dev, struct rt_rtmp_adapter *pAd)
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{
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u16 device_id;
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struct os_cookie *pObj;
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pObj = (struct os_cookie *)pAd->OS_Cookie;
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pci_read_config_word(pci_dev, PCI_DEVICE_ID, &device_id);
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device_id = le2cpu16(device_id);
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pObj->DeviceID = device_id;
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if (
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#ifdef RT2860
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(device_id == NIC2860_PCIe_DEVICE_ID) ||
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(device_id == NIC2790_PCIe_DEVICE_ID) ||
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(device_id == VEN_AWT_PCIe_DEVICE_ID) ||
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#endif
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#ifdef RT3090
|
|
(device_id == NIC3090_PCIe_DEVICE_ID) ||
|
|
(device_id == NIC3091_PCIe_DEVICE_ID) ||
|
|
(device_id == NIC3092_PCIe_DEVICE_ID) ||
|
|
#endif /* RT3090 // */
|
|
0) {
|
|
u32 MacCsr0 = 0, Index = 0;
|
|
do {
|
|
RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0);
|
|
|
|
if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF))
|
|
break;
|
|
|
|
RTMPusecDelay(10);
|
|
} while (Index++ < 100);
|
|
|
|
/* Support advanced power save after 2892/2790. */
|
|
/* MAC version at offset 0x1000 is 0x2872XXXX/0x2870XXXX(PCIe, USB, SDIO). */
|
|
if ((MacCsr0 & 0xffff0000) != 0x28600000)
|
|
OPSTATUS_SET_FLAG(pAd, fOP_STATUS_PCIE_DEVICE);
|
|
}
|
|
}
|
|
|
|
void RTMPInitPCIeLinkCtrlValue(struct rt_rtmp_adapter *pAd)
|
|
{
|
|
int pos;
|
|
u16 reg16, data2, PCIePowerSaveLevel, Configuration;
|
|
u32 MacValue;
|
|
BOOLEAN bFindIntel = FALSE;
|
|
struct os_cookie *pObj;
|
|
|
|
pObj = (struct os_cookie *)pAd->OS_Cookie;
|
|
|
|
if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE))
|
|
return;
|
|
|
|
DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __func__));
|
|
/* Init EEPROM, and save settings */
|
|
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))) {
|
|
RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel);
|
|
pAd->PCIePowerSaveLevel = PCIePowerSaveLevel & 0xff;
|
|
|
|
pAd->LnkCtrlBitMask = 0;
|
|
if ((PCIePowerSaveLevel & 0xff) == 0xff) {
|
|
OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_PCIE_DEVICE);
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("====> PCIePowerSaveLevel = 0x%x.\n",
|
|
PCIePowerSaveLevel));
|
|
return;
|
|
} else {
|
|
PCIePowerSaveLevel &= 0x3;
|
|
RT28xx_EEPROM_READ16(pAd, 0x24, data2);
|
|
|
|
if (!
|
|
(((data2 & 0xff00) == 0x9200)
|
|
&& ((data2 & 0x80) != 0))) {
|
|
if (PCIePowerSaveLevel > 1)
|
|
PCIePowerSaveLevel = 1;
|
|
}
|
|
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("====> Write 0x83 = 0x%x.\n",
|
|
PCIePowerSaveLevel));
|
|
AsicSendCommandToMcu(pAd, 0x83, 0xff,
|
|
(u8)PCIePowerSaveLevel, 0x00);
|
|
RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel);
|
|
PCIePowerSaveLevel &= 0xff;
|
|
PCIePowerSaveLevel = PCIePowerSaveLevel >> 6;
|
|
switch (PCIePowerSaveLevel) {
|
|
case 0: /* Only support L0 */
|
|
pAd->LnkCtrlBitMask = 0;
|
|
break;
|
|
case 1: /* Only enable L0s */
|
|
pAd->LnkCtrlBitMask = 1;
|
|
break;
|
|
case 2: /* enable L1, L0s */
|
|
pAd->LnkCtrlBitMask = 3;
|
|
break;
|
|
case 3: /* sync with host clk and enable L1, L0s */
|
|
pAd->LnkCtrlBitMask = 0x103;
|
|
break;
|
|
}
|
|
RT28xx_EEPROM_READ16(pAd, 0x24, data2);
|
|
if ((PCIePowerSaveLevel & 0xff) != 0xff) {
|
|
PCIePowerSaveLevel &= 0x3;
|
|
|
|
if (!
|
|
(((data2 & 0xff00) == 0x9200)
|
|
&& ((data2 & 0x80) != 0))) {
|
|
if (PCIePowerSaveLevel > 1)
|
|
PCIePowerSaveLevel = 1;
|
|
}
|
|
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("====> rt28xx Write 0x83 Command = 0x%x.\n",
|
|
PCIePowerSaveLevel));
|
|
|
|
AsicSendCommandToMcu(pAd, 0x83, 0xff,
|
|
(u8)PCIePowerSaveLevel,
|
|
0x00);
|
|
}
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("====> LnkCtrlBitMask = 0x%x.\n",
|
|
pAd->LnkCtrlBitMask));
|
|
}
|
|
} else if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) {
|
|
u8 LinkCtrlSetting = 0;
|
|
|
|
/* Check 3090E special setting chip. */
|
|
RT28xx_EEPROM_READ16(pAd, 0x24, data2);
|
|
if ((data2 == 0x9280) && ((pAd->MACVersion & 0xffff) == 0x0211)) {
|
|
pAd->b3090ESpecialChip = TRUE;
|
|
DBGPRINT_RAW(RT_DEBUG_ERROR, ("Special 3090E chip \n"));
|
|
}
|
|
|
|
RTMP_IO_READ32(pAd, AUX_CTRL, &MacValue);
|
|
/*enable WAKE_PCIE function, which forces to enable PCIE clock when mpu interrupt asserting. */
|
|
/*Force PCIE 125MHz CLK to toggle */
|
|
MacValue |= 0x402;
|
|
RTMP_IO_WRITE32(pAd, AUX_CTRL, MacValue);
|
|
DBGPRINT_RAW(RT_DEBUG_ERROR,
|
|
(" AUX_CTRL = 0x%32x\n", MacValue));
|
|
|
|
/* for RT30xx F and after, PCIe interface, and for power solution 3 */
|
|
if ((IS_VERSION_AFTER_F(pAd))
|
|
&& (pAd->StaCfg.PSControl.field.rt30xxPowerMode >= 2)
|
|
&& (pAd->StaCfg.PSControl.field.rt30xxPowerMode <= 3)) {
|
|
RTMP_IO_READ32(pAd, AUX_CTRL, &MacValue);
|
|
DBGPRINT_RAW(RT_DEBUG_ERROR,
|
|
(" Read AUX_CTRL = 0x%x\n", MacValue));
|
|
/* turn on bit 12. */
|
|
/*enable 32KHz clock mode for power saving */
|
|
MacValue |= 0x1000;
|
|
if (MacValue != 0xffffffff) {
|
|
RTMP_IO_WRITE32(pAd, AUX_CTRL, MacValue);
|
|
DBGPRINT_RAW(RT_DEBUG_ERROR,
|
|
(" Write AUX_CTRL = 0x%x\n",
|
|
MacValue));
|
|
/* 1. if use PCIePowerSetting is 2 or 3, need to program OSC_CTRL to 0x3ff11. */
|
|
MacValue = 0x3ff11;
|
|
RTMP_IO_WRITE32(pAd, OSC_CTRL, MacValue);
|
|
DBGPRINT_RAW(RT_DEBUG_ERROR,
|
|
(" OSC_CTRL = 0x%x\n", MacValue));
|
|
/* 2. Write PCI register Clk ref bit */
|
|
RTMPrt3xSetPCIePowerLinkCtrl(pAd);
|
|
} else {
|
|
/* Error read Aux_Ctrl value. Force to use solution 1 */
|
|
DBGPRINT(RT_DEBUG_ERROR,
|
|
(" Error Value in AUX_CTRL = 0x%x\n",
|
|
MacValue));
|
|
pAd->StaCfg.PSControl.field.rt30xxPowerMode = 1;
|
|
DBGPRINT(RT_DEBUG_ERROR,
|
|
(" Force to use power solution1 \n"));
|
|
}
|
|
}
|
|
/* 1. read setting from inf file. */
|
|
|
|
PCIePowerSaveLevel =
|
|
(u16)pAd->StaCfg.PSControl.field.rt30xxPowerMode;
|
|
DBGPRINT(RT_DEBUG_ERROR,
|
|
("====> rt30xx Read PowerLevelMode = 0x%x.\n",
|
|
PCIePowerSaveLevel));
|
|
/* 2. Check EnableNewPS. */
|
|
if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
|
|
PCIePowerSaveLevel = 1;
|
|
|
|
if (IS_VERSION_BEFORE_F(pAd)
|
|
&& (pAd->b3090ESpecialChip == FALSE)) {
|
|
/* Chip Version E only allow 1, So force set 1. */
|
|
PCIePowerSaveLevel &= 0x1;
|
|
pAd->PCIePowerSaveLevel = (u16)PCIePowerSaveLevel;
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("====> rt30xx E Write 0x83 Command = 0x%x.\n",
|
|
PCIePowerSaveLevel));
|
|
|
|
AsicSendCommandToMcu(pAd, 0x83, 0xff,
|
|
(u8)PCIePowerSaveLevel, 0x00);
|
|
} else {
|
|
/* Chip Version F and after only allow 1 or 2 or 3. This might be modified after new chip version come out. */
|
|
if (!
|
|
((PCIePowerSaveLevel == 1)
|
|
|| (PCIePowerSaveLevel == 3)))
|
|
PCIePowerSaveLevel = 1;
|
|
DBGPRINT(RT_DEBUG_ERROR,
|
|
("====> rt30xx F Write 0x83 Command = 0x%x.\n",
|
|
PCIePowerSaveLevel));
|
|
pAd->PCIePowerSaveLevel = (u16)PCIePowerSaveLevel;
|
|
/* for 3090F , we need to add high-byte arg for 0x83 command to indicate the link control setting in */
|
|
/* PCI Configuration Space. Because firmware can't read PCI Configuration Space */
|
|
if ((pAd->Rt3xxRalinkLinkCtrl & 0x2)
|
|
&& (pAd->Rt3xxHostLinkCtrl & 0x2)) {
|
|
LinkCtrlSetting = 1;
|
|
}
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("====> rt30xxF LinkCtrlSetting = 0x%x.\n",
|
|
LinkCtrlSetting));
|
|
AsicSendCommandToMcu(pAd, 0x83, 0xff,
|
|
(u8)PCIePowerSaveLevel,
|
|
LinkCtrlSetting);
|
|
}
|
|
}
|
|
/* Find Ralink PCIe Device's Express Capability Offset */
|
|
pos = pci_find_capability(pObj->pci_dev, PCI_CAP_ID_EXP);
|
|
|
|
if (pos != 0) {
|
|
/* Ralink PCIe Device's Link Control Register Offset */
|
|
pAd->RLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
|
|
pci_read_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset,
|
|
®16);
|
|
Configuration = le2cpu16(reg16);
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("Read (Ralink PCIe Link Control Register) offset 0x%x = 0x%x\n",
|
|
pAd->RLnkCtrlOffset, Configuration));
|
|
pAd->RLnkCtrlConfiguration = (Configuration & 0x103);
|
|
Configuration &= 0xfefc;
|
|
Configuration |= (0x0);
|
|
#ifdef RT2860
|
|
if ((pObj->DeviceID == NIC2860_PCIe_DEVICE_ID)
|
|
|| (pObj->DeviceID == NIC2790_PCIe_DEVICE_ID)) {
|
|
reg16 = cpu2le16(Configuration);
|
|
pci_write_config_word(pObj->pci_dev,
|
|
pAd->RLnkCtrlOffset, reg16);
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("Write (Ralink PCIe Link Control Register) offset 0x%x = 0x%x\n",
|
|
pos + PCI_EXP_LNKCTL, Configuration));
|
|
}
|
|
#endif /* RT2860 // */
|
|
|
|
RTMPFindHostPCIDev(pAd);
|
|
if (pObj->parent_pci_dev) {
|
|
u16 vendor_id;
|
|
|
|
pci_read_config_word(pObj->parent_pci_dev,
|
|
PCI_VENDOR_ID, &vendor_id);
|
|
vendor_id = le2cpu16(vendor_id);
|
|
if (vendor_id == PCIBUS_INTEL_VENDOR) {
|
|
bFindIntel = TRUE;
|
|
RTMP_SET_PSFLAG(pAd, fRTMP_PS_TOGGLE_L1);
|
|
}
|
|
/* Find PCI-to-PCI Bridge Express Capability Offset */
|
|
pos =
|
|
pci_find_capability(pObj->parent_pci_dev,
|
|
PCI_CAP_ID_EXP);
|
|
|
|
if (pos != 0) {
|
|
BOOLEAN bChange = FALSE;
|
|
/* PCI-to-PCI Bridge Link Control Register Offset */
|
|
pAd->HostLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
|
|
pci_read_config_word(pObj->parent_pci_dev,
|
|
pAd->HostLnkCtrlOffset,
|
|
®16);
|
|
Configuration = le2cpu16(reg16);
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("Read (Host PCI-to-PCI Bridge Link Control Register) offset 0x%x = 0x%x\n",
|
|
pAd->HostLnkCtrlOffset,
|
|
Configuration));
|
|
pAd->HostLnkCtrlConfiguration =
|
|
(Configuration & 0x103);
|
|
Configuration &= 0xfefc;
|
|
Configuration |= (0x0);
|
|
|
|
switch (pObj->DeviceID) {
|
|
#ifdef RT2860
|
|
case NIC2860_PCIe_DEVICE_ID:
|
|
case NIC2790_PCIe_DEVICE_ID:
|
|
bChange = TRUE;
|
|
break;
|
|
#endif /* RT2860 // */
|
|
#ifdef RT3090
|
|
case NIC3090_PCIe_DEVICE_ID:
|
|
case NIC3091_PCIe_DEVICE_ID:
|
|
case NIC3092_PCIe_DEVICE_ID:
|
|
if (bFindIntel == FALSE)
|
|
bChange = TRUE;
|
|
break;
|
|
#endif /* RT3090 // */
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (bChange) {
|
|
reg16 = cpu2le16(Configuration);
|
|
pci_write_config_word(pObj->
|
|
parent_pci_dev,
|
|
pAd->
|
|
HostLnkCtrlOffset,
|
|
reg16);
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("Write (Host PCI-to-PCI Bridge Link Control Register) offset 0x%x = 0x%x\n",
|
|
pAd->HostLnkCtrlOffset,
|
|
Configuration));
|
|
}
|
|
} else {
|
|
pAd->HostLnkCtrlOffset = 0;
|
|
DBGPRINT(RT_DEBUG_ERROR,
|
|
("%s: cannot find PCI-to-PCI Bridge PCI Express Capability!\n",
|
|
__func__));
|
|
}
|
|
}
|
|
} else {
|
|
pAd->RLnkCtrlOffset = 0;
|
|
pAd->HostLnkCtrlOffset = 0;
|
|
DBGPRINT(RT_DEBUG_ERROR,
|
|
("%s: cannot find Ralink PCIe Device's PCI Express Capability!\n",
|
|
__func__));
|
|
}
|
|
|
|
if (bFindIntel == FALSE) {
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("Doesn't find Intel PCI host controller. \n"));
|
|
/* Doesn't switch L0, L1, So set PCIePowerSaveLevel to 0xff */
|
|
pAd->PCIePowerSaveLevel = 0xff;
|
|
if ((pAd->RLnkCtrlOffset != 0)
|
|
#ifdef RT3090
|
|
&& ((pObj->DeviceID == NIC3090_PCIe_DEVICE_ID)
|
|
|| (pObj->DeviceID == NIC3091_PCIe_DEVICE_ID)
|
|
|| (pObj->DeviceID == NIC3092_PCIe_DEVICE_ID))
|
|
#endif /* RT3090 // */
|
|
) {
|
|
pci_read_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset,
|
|
®16);
|
|
Configuration = le2cpu16(reg16);
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("Read (Ralink 30xx PCIe Link Control Register) offset 0x%x = 0x%x\n",
|
|
pAd->RLnkCtrlOffset, Configuration));
|
|
pAd->RLnkCtrlConfiguration = (Configuration & 0x103);
|
|
Configuration &= 0xfefc;
|
|
Configuration |= (0x0);
|
|
reg16 = cpu2le16(Configuration);
|
|
pci_write_config_word(pObj->pci_dev,
|
|
pAd->RLnkCtrlOffset, reg16);
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("Write (Ralink PCIe Link Control Register) offset 0x%x = 0x%x\n",
|
|
pos + PCI_EXP_LNKCTL, Configuration));
|
|
}
|
|
}
|
|
}
|
|
|
|
void RTMPFindHostPCIDev(struct rt_rtmp_adapter *pAd)
|
|
{
|
|
u16 reg16;
|
|
u8 reg8;
|
|
u32 DevFn;
|
|
struct pci_dev *pPci_dev;
|
|
struct os_cookie *pObj;
|
|
|
|
pObj = (struct os_cookie *)pAd->OS_Cookie;
|
|
|
|
if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE))
|
|
return;
|
|
|
|
DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __func__));
|
|
|
|
pObj->parent_pci_dev = NULL;
|
|
if (pObj->pci_dev->bus->parent) {
|
|
for (DevFn = 0; DevFn < 255; DevFn++) {
|
|
pPci_dev =
|
|
pci_get_slot(pObj->pci_dev->bus->parent, DevFn);
|
|
if (pPci_dev) {
|
|
pci_read_config_word(pPci_dev, PCI_CLASS_DEVICE,
|
|
®16);
|
|
reg16 = le2cpu16(reg16);
|
|
pci_read_config_byte(pPci_dev, PCI_CB_CARD_BUS,
|
|
®8);
|
|
if ((reg16 == PCI_CLASS_BRIDGE_PCI)
|
|
&& (reg8 == pObj->pci_dev->bus->number)) {
|
|
pObj->parent_pci_dev = pPci_dev;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
========================================================================
|
|
|
|
Routine Description:
|
|
|
|
Arguments:
|
|
Level = RESTORE_HALT : Restore PCI host and Ralink PCIe Link Control field to its default value.
|
|
Level = Other Value : Restore from dot11 power save or radio off status. And force PCI host Link Control fields to 0x1
|
|
|
|
========================================================================
|
|
*/
|
|
void RTMPPCIeLinkCtrlValueRestore(struct rt_rtmp_adapter *pAd, u8 Level)
|
|
{
|
|
u16 PCIePowerSaveLevel, reg16;
|
|
u16 Configuration;
|
|
struct os_cookie *pObj;
|
|
|
|
pObj = (struct os_cookie *)pAd->OS_Cookie;
|
|
|
|
if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE))
|
|
return;
|
|
|
|
#ifdef RT2860
|
|
if (!((pObj->DeviceID == NIC2860_PCIe_DEVICE_ID)
|
|
|| (pObj->DeviceID == NIC2790_PCIe_DEVICE_ID)))
|
|
return;
|
|
#endif /* RT2860 // */
|
|
/* Check PSControl Configuration */
|
|
if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
|
|
return;
|
|
|
|
/*3090 will not execute the following codes. */
|
|
/* Check interface : If not PCIe interface, return. */
|
|
|
|
#ifdef RT3090
|
|
if ((pObj->DeviceID == NIC3090_PCIe_DEVICE_ID)
|
|
|| (pObj->DeviceID == NIC3091_PCIe_DEVICE_ID)
|
|
|| (pObj->DeviceID == NIC3092_PCIe_DEVICE_ID))
|
|
return;
|
|
#endif /* RT3090 // */
|
|
|
|
DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __func__));
|
|
PCIePowerSaveLevel = pAd->PCIePowerSaveLevel;
|
|
if ((PCIePowerSaveLevel & 0xff) == 0xff) {
|
|
DBGPRINT(RT_DEBUG_TRACE, ("return \n"));
|
|
return;
|
|
}
|
|
|
|
if (pObj->parent_pci_dev && (pAd->HostLnkCtrlOffset != 0)) {
|
|
PCI_REG_READ_WORD(pObj->parent_pci_dev, pAd->HostLnkCtrlOffset,
|
|
Configuration);
|
|
if ((Configuration != 0) && (Configuration != 0xFFFF)) {
|
|
Configuration &= 0xfefc;
|
|
/* If call from interface down, restore to original setting. */
|
|
if (Level == RESTORE_CLOSE)
|
|
Configuration |= pAd->HostLnkCtrlConfiguration;
|
|
else
|
|
Configuration |= 0x0;
|
|
PCI_REG_WIRTE_WORD(pObj->parent_pci_dev,
|
|
pAd->HostLnkCtrlOffset,
|
|
Configuration);
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("Restore PCI host : offset 0x%x = 0x%x\n",
|
|
pAd->HostLnkCtrlOffset, Configuration));
|
|
} else
|
|
DBGPRINT(RT_DEBUG_ERROR,
|
|
("Restore PCI host : PCI_REG_READ_WORD failed (Configuration = 0x%x)\n",
|
|
Configuration));
|
|
}
|
|
|
|
if (pObj->pci_dev && (pAd->RLnkCtrlOffset != 0)) {
|
|
PCI_REG_READ_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset,
|
|
Configuration);
|
|
if ((Configuration != 0) && (Configuration != 0xFFFF)) {
|
|
Configuration &= 0xfefc;
|
|
/* If call from interface down, restore to original setting. */
|
|
if (Level == RESTORE_CLOSE)
|
|
Configuration |= pAd->RLnkCtrlConfiguration;
|
|
else
|
|
Configuration |= 0x0;
|
|
PCI_REG_WIRTE_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset,
|
|
Configuration);
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("Restore Ralink : offset 0x%x = 0x%x\n",
|
|
pAd->RLnkCtrlOffset, Configuration));
|
|
} else
|
|
DBGPRINT(RT_DEBUG_ERROR,
|
|
("Restore Ralink : PCI_REG_READ_WORD failed (Configuration = 0x%x)\n",
|
|
Configuration));
|
|
}
|
|
|
|
DBGPRINT(RT_DEBUG_TRACE, ("%s <===\n", __func__));
|
|
}
|
|
|
|
/*
|
|
========================================================================
|
|
|
|
Routine Description:
|
|
|
|
Arguments:
|
|
Max : limit Host PCI and Ralink PCIe device's LINK CONTROL field's value.
|
|
Because now frequently set our device to mode 1 or mode 3 will cause problem.
|
|
|
|
========================================================================
|
|
*/
|
|
void RTMPPCIeLinkCtrlSetting(struct rt_rtmp_adapter *pAd, u16 Max)
|
|
{
|
|
u16 PCIePowerSaveLevel, reg16;
|
|
u16 Configuration;
|
|
struct os_cookie *pObj;
|
|
|
|
pObj = (struct os_cookie *)pAd->OS_Cookie;
|
|
|
|
if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE))
|
|
return;
|
|
|
|
#ifdef RT2860
|
|
if (!((pObj->DeviceID == NIC2860_PCIe_DEVICE_ID)
|
|
|| (pObj->DeviceID == NIC2790_PCIe_DEVICE_ID)))
|
|
return;
|
|
#endif /* RT2860 // */
|
|
/* Check PSControl Configuration */
|
|
if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
|
|
return;
|
|
|
|
/* Check interface : If not PCIe interface, return. */
|
|
/*Block 3090 to enter the following function */
|
|
|
|
#ifdef RT3090
|
|
if ((pObj->DeviceID == NIC3090_PCIe_DEVICE_ID)
|
|
|| (pObj->DeviceID == NIC3091_PCIe_DEVICE_ID)
|
|
|| (pObj->DeviceID == NIC3092_PCIe_DEVICE_ID))
|
|
return;
|
|
#endif /* RT3090 // */
|
|
if (!RTMP_TEST_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP)) {
|
|
DBGPRINT(RT_DEBUG_INFO,
|
|
("RTMPPCIePowerLinkCtrl return on fRTMP_PS_CAN_GO_SLEEP flag\n"));
|
|
return;
|
|
}
|
|
|
|
DBGPRINT(RT_DEBUG_TRACE, ("%s===>\n", __func__));
|
|
PCIePowerSaveLevel = pAd->PCIePowerSaveLevel;
|
|
if ((PCIePowerSaveLevel & 0xff) == 0xff) {
|
|
DBGPRINT(RT_DEBUG_TRACE, ("return \n"));
|
|
return;
|
|
}
|
|
PCIePowerSaveLevel = PCIePowerSaveLevel >> 6;
|
|
|
|
/* Skip non-exist deice right away */
|
|
if (pObj->parent_pci_dev && (pAd->HostLnkCtrlOffset != 0)) {
|
|
PCI_REG_READ_WORD(pObj->parent_pci_dev, pAd->HostLnkCtrlOffset,
|
|
Configuration);
|
|
switch (PCIePowerSaveLevel) {
|
|
case 0:
|
|
/* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 00 */
|
|
Configuration &= 0xfefc;
|
|
break;
|
|
case 1:
|
|
/* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 01 */
|
|
Configuration &= 0xfefc;
|
|
Configuration |= 0x1;
|
|
break;
|
|
case 2:
|
|
/* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 */
|
|
Configuration &= 0xfefc;
|
|
Configuration |= 0x3;
|
|
break;
|
|
case 3:
|
|
/* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 and bit 8 of LinkControl of 2892 to 1 */
|
|
Configuration &= 0xfefc;
|
|
Configuration |= 0x103;
|
|
break;
|
|
}
|
|
PCI_REG_WIRTE_WORD(pObj->parent_pci_dev, pAd->HostLnkCtrlOffset,
|
|
Configuration);
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("Write PCI host offset 0x%x = 0x%x\n",
|
|
pAd->HostLnkCtrlOffset, Configuration));
|
|
}
|
|
|
|
if (pObj->pci_dev && (pAd->RLnkCtrlOffset != 0)) {
|
|
/* first 2892 chip not allow to frequently set mode 3. will cause hang problem. */
|
|
if (PCIePowerSaveLevel > Max)
|
|
PCIePowerSaveLevel = Max;
|
|
|
|
PCI_REG_READ_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset,
|
|
Configuration);
|
|
switch (PCIePowerSaveLevel) {
|
|
case 0:
|
|
/* No PCI power safe */
|
|
/* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 00 . */
|
|
Configuration &= 0xfefc;
|
|
break;
|
|
case 1:
|
|
/* L0 */
|
|
/* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 01 . */
|
|
Configuration &= 0xfefc;
|
|
Configuration |= 0x1;
|
|
break;
|
|
case 2:
|
|
/* L0 and L1 */
|
|
/* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 */
|
|
Configuration &= 0xfefc;
|
|
Configuration |= 0x3;
|
|
break;
|
|
case 3:
|
|
/* L0 , L1 and clock management. */
|
|
/* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 and bit 8 of LinkControl of 2892 to 1 */
|
|
Configuration &= 0xfefc;
|
|
Configuration |= 0x103;
|
|
pAd->bPCIclkOff = TRUE;
|
|
break;
|
|
}
|
|
PCI_REG_WIRTE_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset,
|
|
Configuration);
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("Write Ralink device : offset 0x%x = 0x%x\n",
|
|
pAd->RLnkCtrlOffset, Configuration));
|
|
}
|
|
|
|
DBGPRINT(RT_DEBUG_TRACE, ("RTMPPCIePowerLinkCtrl <==============\n"));
|
|
}
|
|
|
|
/*
|
|
========================================================================
|
|
|
|
Routine Description:
|
|
1. Write a PCI register for rt30xx power solution 3
|
|
|
|
========================================================================
|
|
*/
|
|
void RTMPrt3xSetPCIePowerLinkCtrl(struct rt_rtmp_adapter *pAd)
|
|
{
|
|
|
|
unsigned long HostConfiguration = 0;
|
|
unsigned long Configuration;
|
|
struct os_cookie *pObj;
|
|
int pos;
|
|
u16 reg16;
|
|
|
|
pObj = (struct os_cookie *)pAd->OS_Cookie;
|
|
|
|
DBGPRINT(RT_DEBUG_INFO,
|
|
("RTMPrt3xSetPCIePowerLinkCtrl.===> %lx\n",
|
|
pAd->StaCfg.PSControl.word));
|
|
|
|
/* Check PSControl Configuration */
|
|
if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
|
|
return;
|
|
RTMPFindHostPCIDev(pAd);
|
|
if (pObj->parent_pci_dev) {
|
|
/* Find PCI-to-PCI Bridge Express Capability Offset */
|
|
pos = pci_find_capability(pObj->parent_pci_dev, PCI_CAP_ID_EXP);
|
|
|
|
if (pos != 0)
|
|
pAd->HostLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
|
|
|
|
/* If configured to turn on L1. */
|
|
HostConfiguration = 0;
|
|
if (pAd->StaCfg.PSControl.field.rt30xxForceASPMTest == 1) {
|
|
DBGPRINT(RT_DEBUG_TRACE, ("Enter,PSM : Force ASPM\n"));
|
|
|
|
/* Skip non-exist device right away */
|
|
if ((pAd->HostLnkCtrlOffset != 0)) {
|
|
PCI_REG_READ_WORD(pObj->parent_pci_dev,
|
|
pAd->HostLnkCtrlOffset,
|
|
HostConfiguration);
|
|
/* Prepare Configuration to write to Host */
|
|
HostConfiguration |= 0x3;
|
|
PCI_REG_WIRTE_WORD(pObj->parent_pci_dev,
|
|
pAd->HostLnkCtrlOffset,
|
|
HostConfiguration);
|
|
pAd->Rt3xxHostLinkCtrl = HostConfiguration;
|
|
/* Because in rt30xxForceASPMTest Mode, Force turn on L0s, L1. */
|
|
/* Fix HostConfiguration bit0:1 = 0x3 for later use. */
|
|
HostConfiguration = 0x3;
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("PSM : Force ASPM : "
|
|
"Host device L1/L0s Value = 0x%lx\n",
|
|
HostConfiguration));
|
|
}
|
|
} else if (pAd->StaCfg.PSControl.field.rt30xxFollowHostASPM ==
|
|
1) {
|
|
|
|
/* Skip non-exist deice right away */
|
|
if ((pAd->HostLnkCtrlOffset != 0)) {
|
|
PCI_REG_READ_WORD(pObj->parent_pci_dev,
|
|
pAd->HostLnkCtrlOffset,
|
|
HostConfiguration);
|
|
pAd->Rt3xxHostLinkCtrl = HostConfiguration;
|
|
HostConfiguration &= 0x3;
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("PSM : Follow Host ASPM : "
|
|
"Host device L1/L0s Value = 0x%lx\n",
|
|
HostConfiguration));
|
|
}
|
|
}
|
|
}
|
|
/* Prepare to write Ralink setting. */
|
|
/* Find Ralink PCIe Device's Express Capability Offset */
|
|
pos = pci_find_capability(pObj->pci_dev, PCI_CAP_ID_EXP);
|
|
|
|
if (pos != 0) {
|
|
/* Ralink PCIe Device's Link Control Register Offset */
|
|
pAd->RLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
|
|
pci_read_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset,
|
|
®16);
|
|
Configuration = le2cpu16(reg16);
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("Read (Ralink PCIe Link Control Register) "
|
|
"offset 0x%x = 0x%lx\n",
|
|
pAd->RLnkCtrlOffset, Configuration));
|
|
Configuration |= 0x100;
|
|
if ((pAd->StaCfg.PSControl.field.rt30xxFollowHostASPM == 1)
|
|
|| (pAd->StaCfg.PSControl.field.rt30xxForceASPMTest == 1)) {
|
|
switch (HostConfiguration) {
|
|
case 0:
|
|
Configuration &= 0xffffffc;
|
|
break;
|
|
case 1:
|
|
Configuration &= 0xffffffc;
|
|
Configuration |= 0x1;
|
|
break;
|
|
case 2:
|
|
Configuration &= 0xffffffc;
|
|
Configuration |= 0x2;
|
|
break;
|
|
case 3:
|
|
Configuration |= 0x3;
|
|
break;
|
|
}
|
|
}
|
|
reg16 = cpu2le16(Configuration);
|
|
pci_write_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset,
|
|
reg16);
|
|
pAd->Rt3xxRalinkLinkCtrl = Configuration;
|
|
DBGPRINT(RT_DEBUG_TRACE,
|
|
("PSM :Write Ralink device L1/L0s Value = 0x%lx\n",
|
|
Configuration));
|
|
}
|
|
DBGPRINT(RT_DEBUG_INFO,
|
|
("PSM :RTMPrt3xSetPCIePowerLinkCtrl <==============\n"));
|
|
}
|