93e85d8e90
CNS3xxx SOCs have L310-compatible cache controller, so let's use it. With this patch benchmarking with 'gzip' shows that performance is doubled, and I'm still able to boot full-fledged userland over NFS (using PCIe NIC), so the support should be pretty robust. p.s. While CNS3xxx reports that it has PL310, it still needs to wait on cache line operations, so we should not select 'CACHE_PL310', which is a micro-optimization that removes these waits for v7 CPUs. Someday we'd better rename CACHE_PL310 Kconfig option into NO_CACHE_WAIT or something less ambiguous. Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
26 lines
671 B
C
26 lines
671 B
C
/*
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* Copyright 2000 Deep Blue Solutions Ltd
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* Copyright 2004 ARM Limited
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* Copyright 2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*/
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#ifndef __CNS3XXX_CORE_H
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#define __CNS3XXX_CORE_H
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extern struct sys_timer cns3xxx_timer;
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#ifdef CONFIG_CACHE_L2X0
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void __init cns3xxx_l2x0_init(void);
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#else
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static inline void cns3xxx_l2x0_init(void) {}
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#endif /* CONFIG_CACHE_L2X0 */
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void __init cns3xxx_map_io(void);
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void __init cns3xxx_init_irq(void);
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void cns3xxx_power_off(void);
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#endif /* __CNS3XXX_CORE_H */
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