ed1f31b4b7
IRQ assignments are different for MSM8X60 than other existing MSMs. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
28 lines
870 B
C
28 lines
870 B
C
/* Copyright (c) 2010 Code Aurora Forum. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ASM_ARCH_MSM_IRQS_8X60_H
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#define __ASM_ARCH_MSM_IRQS_8X60_H
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/* MSM ACPU Interrupt Numbers */
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/* 0-15: STI/SGI (software triggered/generated interrupts)
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* 16-31: PPI (private peripheral interrupts)
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* 32+: SPI (shared peripheral interrupts)
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*/
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#define NR_GPIO_IRQS 173
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#define NR_MSM_IRQS 256
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#define NR_BOARD_IRQS 0
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#endif
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