b55f685e97
This patch adds support System MMU which supports address transition from virtual address to physical address. Basically, each hardware block is connected System MMU block can use directly vitrual address when it accesses physical memory not using physical address. Signed-off-by: Donguk Ryu <du.ryu@samsung.com> Signed-off-by: Sangbeom Kim <sbkim73@samsung.com> [kgene.kim@samsung.com: removed useless codes] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
146 lines
4.3 KiB
C
146 lines
4.3 KiB
C
/* linux/arch/arm/mach-s5pv310/include/mach/irqs.h
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5PV310 - IRQ definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_IRQS_H
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#define __ASM_ARCH_IRQS_H __FILE__
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#include <plat/irqs.h>
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/* PPI: Private Peripheral Interrupt */
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#define IRQ_PPI(x) S5P_IRQ(x+16)
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#define IRQ_LOCALTIMER IRQ_PPI(13)
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/* SPI: Shared Peripheral Interrupt */
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#define IRQ_SPI(x) S5P_IRQ(x+32)
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#define IRQ_MCT1 IRQ_SPI(35)
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#define IRQ_EINT0 IRQ_SPI(40)
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#define IRQ_EINT1 IRQ_SPI(41)
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#define IRQ_EINT2 IRQ_SPI(42)
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#define IRQ_EINT3 IRQ_SPI(43)
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#define IRQ_USB_HSOTG IRQ_SPI(44)
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#define IRQ_USB_HOST IRQ_SPI(45)
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#define IRQ_MODEM_IF IRQ_SPI(46)
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#define IRQ_ROTATOR IRQ_SPI(47)
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#define IRQ_JPEG IRQ_SPI(48)
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#define IRQ_2D IRQ_SPI(49)
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#define IRQ_PCIE IRQ_SPI(50)
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#define IRQ_MCT0 IRQ_SPI(51)
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#define IRQ_MFC IRQ_SPI(52)
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#define IRQ_AUDIO_SS IRQ_SPI(54)
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#define IRQ_AC97 IRQ_SPI(55)
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#define IRQ_SPDIF IRQ_SPI(56)
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#define IRQ_KEYPAD IRQ_SPI(57)
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#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(58)
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#define IRQ_SLIMBUS IRQ_SPI(59)
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#define IRQ_PMU IRQ_SPI(60)
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#define IRQ_TSI IRQ_SPI(61)
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#define IRQ_SATA IRQ_SPI(62)
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#define IRQ_GPS IRQ_SPI(63)
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#define MAX_IRQ_IN_COMBINER 8
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#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64))
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#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
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#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
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#define IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
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#define IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
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#define IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
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#define IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
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#define IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
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#define IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
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#define IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
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#define IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
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#define IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
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#define IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
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#define IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
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#define IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
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#define IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
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#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
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#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
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#define IRQ_PDMA0 COMBINER_IRQ(21, 0)
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#define IRQ_PDMA1 COMBINER_IRQ(21, 1)
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#define IRQ_TIMER0_VIC COMBINER_IRQ(22, 0)
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#define IRQ_TIMER1_VIC COMBINER_IRQ(22, 1)
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#define IRQ_TIMER2_VIC COMBINER_IRQ(22, 2)
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#define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3)
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#define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4)
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#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0)
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#define IRQ_RTC_TIC COMBINER_IRQ(23, 1)
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#define IRQ_UART0 COMBINER_IRQ(26, 0)
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#define IRQ_UART1 COMBINER_IRQ(26, 1)
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#define IRQ_UART2 COMBINER_IRQ(26, 2)
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#define IRQ_UART3 COMBINER_IRQ(26, 3)
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#define IRQ_UART4 COMBINER_IRQ(26, 4)
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#define IRQ_IIC COMBINER_IRQ(27, 0)
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#define IRQ_IIC1 COMBINER_IRQ(27, 1)
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#define IRQ_IIC2 COMBINER_IRQ(27, 2)
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#define IRQ_IIC3 COMBINER_IRQ(27, 3)
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#define IRQ_IIC4 COMBINER_IRQ(27, 4)
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#define IRQ_IIC5 COMBINER_IRQ(27, 5)
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#define IRQ_IIC6 COMBINER_IRQ(27, 6)
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#define IRQ_IIC7 COMBINER_IRQ(27, 7)
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#define IRQ_HSMMC0 COMBINER_IRQ(29, 0)
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#define IRQ_HSMMC1 COMBINER_IRQ(29, 1)
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#define IRQ_HSMMC2 COMBINER_IRQ(29, 2)
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#define IRQ_HSMMC3 COMBINER_IRQ(29, 3)
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#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0)
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#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1)
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#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
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#define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
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#define IRQ_EINT4 COMBINER_IRQ(37, 0)
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#define IRQ_EINT5 COMBINER_IRQ(37, 1)
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#define IRQ_EINT6 COMBINER_IRQ(37, 2)
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#define IRQ_EINT7 COMBINER_IRQ(37, 3)
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#define IRQ_EINT8 COMBINER_IRQ(38, 0)
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#define IRQ_EINT9 COMBINER_IRQ(38, 1)
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#define IRQ_EINT10 COMBINER_IRQ(38, 2)
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#define IRQ_EINT11 COMBINER_IRQ(38, 3)
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#define IRQ_EINT12 COMBINER_IRQ(38, 4)
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#define IRQ_EINT13 COMBINER_IRQ(38, 5)
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#define IRQ_EINT14 COMBINER_IRQ(38, 6)
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#define IRQ_EINT15 COMBINER_IRQ(38, 7)
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#define IRQ_EINT16_31 COMBINER_IRQ(39, 0)
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#define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
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#define IRQ_WDT COMBINER_IRQ(53, 0)
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#define MAX_COMBINER_NR 54
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#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
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#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0)
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#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16)
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/* Set the default NR_IRQS */
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#define NR_IRQS (S5P_IRQ_EINT_BASE + 32)
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#endif /* __ASM_ARCH_IRQS_H */
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