1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
493 lines
12 KiB
C
493 lines
12 KiB
C
/* Copyright(c) 2000, Compaq Computer Corporation
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* Fibre Channel Host Bus Adapter
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* 64-bit, 66MHz PCI
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* Originally developed and tested on:
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* (front): [chip] Tachyon TS HPFC-5166A/1.2 L2C1090 ...
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* SP# P225CXCBFIEL6T, Rev XC
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* SP# 161290-001, Rev XD
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* (back): Board No. 010008-001 A/W Rev X5, FAB REV X5
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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* Written by Don Zimmerman
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*/
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// These functions control the NVRAM I2C hardware on
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// non-intelligent Fibre Host Adapters.
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// The primary purpose is to read the HBA's NVRAM to get adapter's
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// manufactured WWN to copy into Tachyon chip registers
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// Orignal source author unknown
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#include <linux/types.h>
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enum boolean { FALSE, TRUE } ;
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#ifndef UCHAR
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typedef __u8 UCHAR;
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#endif
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#ifndef BOOLEAN
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typedef __u8 BOOLEAN;
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#endif
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#ifndef USHORT
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typedef __u16 USHORT;
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#endif
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#ifndef ULONG
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typedef __u32 ULONG;
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#endif
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#include <linux/string.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <asm/io.h> // struct pt_regs for IRQ handler & Port I/O
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#include "cpqfcTSchip.h"
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static void tl_i2c_tx_byte( void* GPIOout, UCHAR data );
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/*static BOOLEAN tl_write_i2c_page_portion( void* GPIOin, void* GPIOout,
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USHORT startOffset, // e.g. 0x2f for WWN start
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USHORT count,
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UCHAR *buf );
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*/
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//
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// Tachlite GPIO2, GPIO3 (I2C) DEFINES
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// The NVRAM chip NM24C03 defines SCL (serial clock) and SDA (serial data)
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// GPIO2 drives SDA, and GPIO3 drives SCL
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//
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// Since Tachlite inverts the state of the GPIO 0-3 outputs, SET writes 0
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// and clear writes 1. The input lines (read in TL status) is NOT inverted
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// This really helps confuse the code and debugging.
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#define SET_DATA_HI 0x0
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#define SET_DATA_LO 0x8
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#define SET_CLOCK_HI 0x0
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#define SET_CLOCK_LO 0x4
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#define SENSE_DATA_HI 0x8
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#define SENSE_DATA_LO 0x0
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#define SENSE_CLOCK_HI 0x4
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#define SENSE_CLOCK_LO 0x0
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#define SLAVE_READ_ADDRESS 0xA1
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#define SLAVE_WRITE_ADDRESS 0xA0
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static void i2c_delay(ULONG mstime);
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static void tl_i2c_clock_pulse( UCHAR , void* GPIOout);
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static UCHAR tl_read_i2c_data( void* );
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//-----------------------------------------------------------------------------
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//
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// Name: I2C_RX_ACK
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//
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// This routine receives an acknowledge over the I2C bus.
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//
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//-----------------------------------------------------------------------------
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static unsigned short tl_i2c_rx_ack( void* GPIOin, void* GPIOout )
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{
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unsigned long value;
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// do clock pulse, let data line float high
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tl_i2c_clock_pulse( SET_DATA_HI, GPIOout );
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// slave must drive data low for acknowledge
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value = tl_read_i2c_data( GPIOin);
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if (value & SENSE_DATA_HI )
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return( FALSE );
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return( TRUE );
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}
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//-----------------------------------------------------------------------------
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//
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// Name: READ_I2C_REG
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//
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// This routine reads the I2C control register using the global
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// IO address stored in gpioreg.
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//
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//-----------------------------------------------------------------------------
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static UCHAR tl_read_i2c_data( void* gpioreg )
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{
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return( (UCHAR)(readl( gpioreg ) & 0x08L) ); // GPIO3
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}
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//-----------------------------------------------------------------------------
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//
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// Name: WRITE_I2C_REG
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//
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// This routine writes the I2C control register using the global
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// IO address stored in gpioreg.
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// In Tachlite, we don't want to modify other bits in TL Control reg.
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//
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//-----------------------------------------------------------------------------
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static void tl_write_i2c_reg( void* gpioregOUT, UCHAR value )
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{
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ULONG temp;
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// First read the register and clear out the old bits
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temp = readl( gpioregOUT ) & 0xfffffff3L;
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// Now or in the new data and send it back out
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writel( temp | value, gpioregOUT);
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}
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//-----------------------------------------------------------------------------
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//
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// Name: I2C_TX_START
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//
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// This routine transmits a start condition over the I2C bus.
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// 1. Set SCL (clock, GPIO2) HIGH, set SDA (data, GPIO3) HIGH,
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// wait 5us to stabilize.
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// 2. With SCL still HIGH, drive SDA low. The low transition marks
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// the start condition to NM24Cxx (the chip)
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// NOTE! In TL control reg., output 1 means chip sees LOW
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//
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//-----------------------------------------------------------------------------
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static unsigned short tl_i2c_tx_start( void* GPIOin, void* GPIOout )
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{
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unsigned short i;
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ULONG value;
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if ( !(tl_read_i2c_data(GPIOin) & SENSE_DATA_HI))
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{
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// start with clock high, let data float high
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tl_write_i2c_reg( GPIOout, SET_DATA_HI | SET_CLOCK_HI );
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// keep sending clock pulses if slave is driving data line
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for (i = 0; i < 10; i++)
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{
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tl_i2c_clock_pulse( SET_DATA_HI, GPIOout );
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if ( tl_read_i2c_data(GPIOin) & SENSE_DATA_HI )
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break;
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}
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// if he's still driving data low after 10 clocks, abort
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value = tl_read_i2c_data( GPIOin ); // read status
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if (!(value & 0x08) )
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return( FALSE );
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}
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// To START, bring data low while clock high
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tl_write_i2c_reg( GPIOout, SET_CLOCK_HI | SET_DATA_LO );
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i2c_delay(0);
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return( TRUE ); // TX start successful
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}
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//-----------------------------------------------------------------------------
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//
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// Name: I2C_TX_STOP
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//
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// This routine transmits a stop condition over the I2C bus.
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//
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//-----------------------------------------------------------------------------
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static unsigned short tl_i2c_tx_stop( void* GPIOin, void* GPIOout )
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{
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int i;
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for (i = 0; i < 10; i++)
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{
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// Send clock pulse, drive data line low
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tl_i2c_clock_pulse( SET_DATA_LO, GPIOout );
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// To STOP, bring data high while clock high
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tl_write_i2c_reg( GPIOout, SET_DATA_HI | SET_CLOCK_HI );
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// Give the data line time to float high
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i2c_delay(0);
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// If slave is driving data line low, there's a problem; retry
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if ( tl_read_i2c_data(GPIOin) & SENSE_DATA_HI )
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return( TRUE ); // TX STOP successful!
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}
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return( FALSE ); // error
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}
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//-----------------------------------------------------------------------------
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//
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// Name: I2C_TX_uchar
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//
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// This routine transmits a byte across the I2C bus.
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//
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//-----------------------------------------------------------------------------
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static void tl_i2c_tx_byte( void* GPIOout, UCHAR data )
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{
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UCHAR bit;
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for (bit = 0x80; bit; bit >>= 1)
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{
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if( data & bit )
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tl_i2c_clock_pulse( (UCHAR)SET_DATA_HI, GPIOout);
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else
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tl_i2c_clock_pulse( (UCHAR)SET_DATA_LO, GPIOout);
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}
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}
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//-----------------------------------------------------------------------------
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//
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// Name: I2C_RX_uchar
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//
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// This routine receives a byte across the I2C bus.
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//
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//-----------------------------------------------------------------------------
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static UCHAR tl_i2c_rx_byte( void* GPIOin, void* GPIOout )
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{
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UCHAR bit;
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UCHAR data = 0;
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for (bit = 0x80; bit; bit >>= 1) {
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// do clock pulse, let data line float high
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tl_i2c_clock_pulse( SET_DATA_HI, GPIOout );
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// read data line
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if ( tl_read_i2c_data( GPIOin) & 0x08 )
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data |= bit;
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}
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return (data);
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}
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//*****************************************************************************
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//*****************************************************************************
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// Function: read_i2c_nvram
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// Arguments: UCHAR count number of bytes to read
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// UCHAR *buf area to store the bytes read
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// Returns: 0 - failed
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// 1 - success
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//*****************************************************************************
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//*****************************************************************************
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unsigned long cpqfcTS_ReadNVRAM( void* GPIOin, void* GPIOout , USHORT count,
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UCHAR *buf )
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{
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unsigned short i;
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if( !( tl_i2c_tx_start(GPIOin, GPIOout) ))
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return FALSE;
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// Select the NVRAM for "dummy" write, to set the address
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tl_i2c_tx_byte( GPIOout , SLAVE_WRITE_ADDRESS );
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if ( !tl_i2c_rx_ack(GPIOin, GPIOout ) )
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return( FALSE );
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// Now send the address where we want to start reading
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tl_i2c_tx_byte( GPIOout , 0 );
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if ( !tl_i2c_rx_ack(GPIOin, GPIOout ) )
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return( FALSE );
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// Send a repeated start condition and select the
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// slave for reading now.
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if( tl_i2c_tx_start(GPIOin, GPIOout) )
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tl_i2c_tx_byte( GPIOout, SLAVE_READ_ADDRESS );
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if ( !tl_i2c_rx_ack(GPIOin, GPIOout) )
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return( FALSE );
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// this loop will now read out the data and store it
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// in the buffer pointed to by buf
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for ( i=0; i<count; i++)
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{
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*buf++ = tl_i2c_rx_byte(GPIOin, GPIOout);
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// Send ACK by holding data line low for 1 clock
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if ( i < (count-1) )
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tl_i2c_clock_pulse( 0x08, GPIOout );
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else {
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// Don't send ack for final byte
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tl_i2c_clock_pulse( SET_DATA_HI, GPIOout );
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}
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}
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tl_i2c_tx_stop(GPIOin, GPIOout);
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return( TRUE );
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}
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//****************************************************************
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//
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//
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//
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// routines to set and clear the data and clock bits
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//
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//
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//
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//****************************************************************
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static void tl_set_clock(void* gpioreg)
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{
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ULONG ret_val;
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ret_val = readl( gpioreg );
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ret_val &= 0xffffffFBL; // clear GPIO2 (SCL)
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writel( ret_val, gpioreg);
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}
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static void tl_clr_clock(void* gpioreg)
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{
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ULONG ret_val;
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ret_val = readl( gpioreg );
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ret_val |= SET_CLOCK_LO;
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writel( ret_val, gpioreg);
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}
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//*****************************************************************
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//
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//
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// This routine will advance the clock by one period
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//
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//
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//*****************************************************************
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static void tl_i2c_clock_pulse( UCHAR value, void* GPIOout )
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{
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ULONG ret_val;
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// clear the clock bit
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tl_clr_clock( GPIOout );
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i2c_delay(0);
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// read the port to preserve non-I2C bits
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ret_val = readl( GPIOout );
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// clear the data & clock bits
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ret_val &= 0xFFFFFFf3;
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// write the value passed in...
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// data can only change while clock is LOW!
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ret_val |= value; // the data
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ret_val |= SET_CLOCK_LO; // the clock
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writel( ret_val, GPIOout );
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i2c_delay(0);
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//set clock bit
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tl_set_clock( GPIOout);
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}
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//*****************************************************************
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//
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//
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// This routine returns the 64-bit WWN
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//
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//
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//*****************************************************************
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int cpqfcTS_GetNVRAM_data( UCHAR *wwnbuf, UCHAR *buf )
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{
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ULONG len;
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ULONG sub_len;
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ULONG ptr_inc;
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ULONG i;
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ULONG j;
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UCHAR *data_ptr;
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UCHAR z;
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UCHAR name;
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UCHAR sub_name;
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UCHAR done;
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int iReturn=0; // def. 0 offset is failure to find WWN field
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data_ptr = (UCHAR *)buf;
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done = FALSE;
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i = 0;
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while ( (i < 128) && (!done) )
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{
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z = data_ptr[i];\
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if ( !(z & 0x80) )
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{
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len = 1 + (z & 0x07);
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name = (z & 0x78) >> 3;
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if (name == 0x0F)
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done = TRUE;
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}
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else
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{
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name = z & 0x7F;
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len = 3 + data_ptr[i+1] + (data_ptr[i+2] << 8);
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switch (name)
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{
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case 0x0D:
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//
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j = i + 3;
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//
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if ( data_ptr[j] == 0x3b ) {
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len = 6;
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break;
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}
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while ( j<(i+len) ) {
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sub_name = (data_ptr[j] & 0x3f);
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sub_len = data_ptr[j+1] +
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(data_ptr[j+2] << 8);
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ptr_inc = sub_len + 3;
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switch (sub_name)
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{
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case 0x3C:
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memcpy( wwnbuf, &data_ptr[j+3], 8);
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iReturn = j+3;
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break;
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default:
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break;
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}
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j += ptr_inc;
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}
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break;
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default:
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break;
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}
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}
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//
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i += len;
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} // end while
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return iReturn;
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}
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// define a short 5 micro sec delay, and longer (ms) delay
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static void i2c_delay(ULONG mstime)
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{
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ULONG i;
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// NOTE: we only expect to use these delays when reading
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// our adapter's NVRAM, which happens only during adapter reset.
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// Delay technique from "Linux Device Drivers", A. Rubini
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// (1st Ed.) pg 137.
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// printk(" delay %lx ", mstime);
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if( mstime ) // ms delay?
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{
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// delay technique
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for( i=0; i < mstime; i++)
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udelay(1000); // 1ms per loop
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}
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else // 5 micro sec delay
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udelay( 5 ); // micro secs
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// printk("done\n");
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}
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