b93b2abce4
All Octeon chips can support more than 4GB of RAM. Also due to how Octeon PCI is setup, even some configurations with less than 4GB of RAM will have portions that are not accessible from 32-bit devices. Enable the swiotlb code to handle the cases where a device cannot directly do DMA. This is a complete rewrite of the Octeon DMA mapping code. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1639/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
72 lines
1.5 KiB
C
72 lines
1.5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
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*
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*
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* Similar to mach-generic/dma-coherence.h except
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* plat_device_is_coherent hard coded to return 1.
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*
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*/
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#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
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#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
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struct device;
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extern void octeon_pci_dma_init(void);
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static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
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size_t size)
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{
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BUG();
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}
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static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
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struct page *page)
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{
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BUG();
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}
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static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
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dma_addr_t dma_addr)
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{
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BUG();
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}
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static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
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size_t size, enum dma_data_direction direction)
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{
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BUG();
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}
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static inline int plat_dma_supported(struct device *dev, u64 mask)
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{
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BUG();
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}
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static inline void plat_extra_sync_for_device(struct device *dev)
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{
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BUG();
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}
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static inline int plat_device_is_coherent(struct device *dev)
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{
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return 1;
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}
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static inline int plat_dma_mapping_error(struct device *dev,
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dma_addr_t dma_addr)
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{
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BUG();
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}
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dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
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phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
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struct dma_map_ops;
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extern struct dma_map_ops *octeon_pci_dma_map_ops;
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extern char *octeon_swiotlb;
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#endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */
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