b4bca26c01
Provide support for drivers/char/rtc.c ioctls in the Mostek rtc driver as well as the Sparc specific RTCGET and RTCSET. This allows userspace to be much less messy. Currently util-linux and other spots jump through hoops trying various ioctl variants until it hits the right one whatever driver actually being used supports. Eventually all of this should move over to the genrtc.c driver, but not today... While we are here, fix up the register types for sparse. Thanks to Frans Pop for helping point out this issue. Signed-off-by: David S. Miller <davem@davemloft.net>
144 lines
5.3 KiB
C
144 lines
5.3 KiB
C
/* $Id: mostek.h,v 1.4 2001/01/11 15:07:09 davem Exp $
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* mostek.h: Describes the various Mostek time of day clock registers.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
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*/
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#ifndef _SPARC64_MOSTEK_H
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#define _SPARC64_MOSTEK_H
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#include <asm/idprom.h>
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/* M48T02 Register Map (adapted from Sun NVRAM/Hostid FAQ)
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*
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* Data
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* Address Function
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* Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
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* 7ff - - - - - - - - Year 00-99
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* 7fe 0 0 0 - - - - - Month 01-12
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* 7fd 0 0 - - - - - - Date 01-31
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* 7fc 0 FT 0 0 0 - - - Day 01-07
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* 7fb KS 0 - - - - - - Hours 00-23
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* 7fa 0 - - - - - - - Minutes 00-59
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* 7f9 ST - - - - - - - Seconds 00-59
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* 7f8 W R S - - - - - Control
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*
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* * ST is STOP BIT
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* * W is WRITE BIT
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* * R is READ BIT
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* * S is SIGN BIT
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* * FT is FREQ TEST BIT
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* * KS is KICK START BIT
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*/
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/* The Mostek 48t02 real time clock and NVRAM chip. The registers
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* other than the control register are in binary coded decimal. Some
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* control bits also live outside the control register.
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*
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* We now deal with physical addresses for I/O to the chip. -DaveM
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*/
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static __inline__ u8 mostek_read(void * __iomem addr)
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{
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u8 ret;
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__asm__ __volatile__("lduba [%1] %2, %0"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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static __inline__ void mostek_write(void * __iomem addr, u8 val)
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{
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__asm__ __volatile__("stba %0, [%1] %2"
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: /* no outputs */
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: "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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#define MOSTEK_EEPROM 0x0000UL
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#define MOSTEK_IDPROM 0x07d8UL
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#define MOSTEK_CREG 0x07f8UL
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#define MOSTEK_SEC 0x07f9UL
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#define MOSTEK_MIN 0x07faUL
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#define MOSTEK_HOUR 0x07fbUL
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#define MOSTEK_DOW 0x07fcUL
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#define MOSTEK_DOM 0x07fdUL
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#define MOSTEK_MONTH 0x07feUL
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#define MOSTEK_YEAR 0x07ffUL
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extern spinlock_t mostek_lock;
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extern void *__iomem mstk48t02_regs;
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/* Control register values. */
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#define MSTK_CREG_WRITE 0x80 /* Must set this before placing values. */
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#define MSTK_CREG_READ 0x40 /* Stop updates to allow a clean read. */
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#define MSTK_CREG_SIGN 0x20 /* Slow/speed clock in calibration mode. */
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/* Control bits that live in the other registers. */
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#define MSTK_STOP 0x80 /* Stop the clock oscillator. (sec) */
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#define MSTK_KICK_START 0x80 /* Kick start the clock chip. (hour) */
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#define MSTK_FREQ_TEST 0x40 /* Frequency test mode. (day) */
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#define MSTK_YEAR_ZERO 1968 /* If year reg has zero, it is 1968. */
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#define MSTK_CVT_YEAR(yr) ((yr) + MSTK_YEAR_ZERO)
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/* Masks that define how much space each value takes up. */
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#define MSTK_SEC_MASK 0x7f
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#define MSTK_MIN_MASK 0x7f
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#define MSTK_HOUR_MASK 0x3f
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#define MSTK_DOW_MASK 0x07
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#define MSTK_DOM_MASK 0x3f
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#define MSTK_MONTH_MASK 0x1f
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#define MSTK_YEAR_MASK 0xff
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/* Binary coded decimal conversion macros. */
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#define MSTK_REGVAL_TO_DECIMAL(x) (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
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#define MSTK_DECIMAL_TO_REGVAL(x) ((((x) / 0x0A) << 0x04) + ((x) % 0x0A))
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/* Generic register set and get macros for internal use. */
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#define MSTK_GET(regs,name) \
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(MSTK_REGVAL_TO_DECIMAL(mostek_read(regs + MOSTEK_ ## name) & MSTK_ ## name ## _MASK))
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#define MSTK_SET(regs,name,value) \
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do { u8 __val = mostek_read(regs + MOSTEK_ ## name); \
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__val &= ~(MSTK_ ## name ## _MASK); \
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__val |= (MSTK_DECIMAL_TO_REGVAL(value) & \
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(MSTK_ ## name ## _MASK)); \
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mostek_write(regs + MOSTEK_ ## name, __val); \
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} while(0)
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/* Macros to make register access easier on our fingers. These give you
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* the decimal value of the register requested if applicable. You pass
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* the a pointer to a 'struct mostek48t02'.
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*/
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#define MSTK_REG_CREG(regs) (mostek_read((regs) + MOSTEK_CREG))
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#define MSTK_REG_SEC(regs) MSTK_GET(regs,SEC)
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#define MSTK_REG_MIN(regs) MSTK_GET(regs,MIN)
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#define MSTK_REG_HOUR(regs) MSTK_GET(regs,HOUR)
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#define MSTK_REG_DOW(regs) MSTK_GET(regs,DOW)
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#define MSTK_REG_DOM(regs) MSTK_GET(regs,DOM)
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#define MSTK_REG_MONTH(regs) MSTK_GET(regs,MONTH)
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#define MSTK_REG_YEAR(regs) MSTK_GET(regs,YEAR)
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#define MSTK_SET_REG_SEC(regs,value) MSTK_SET(regs,SEC,value)
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#define MSTK_SET_REG_MIN(regs,value) MSTK_SET(regs,MIN,value)
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#define MSTK_SET_REG_HOUR(regs,value) MSTK_SET(regs,HOUR,value)
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#define MSTK_SET_REG_DOW(regs,value) MSTK_SET(regs,DOW,value)
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#define MSTK_SET_REG_DOM(regs,value) MSTK_SET(regs,DOM,value)
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#define MSTK_SET_REG_MONTH(regs,value) MSTK_SET(regs,MONTH,value)
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#define MSTK_SET_REG_YEAR(regs,value) MSTK_SET(regs,YEAR,value)
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/* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the
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* same (basically) layout of the 48t02 chip except for the extra
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* NVRAM on board (8 KB against the 48t02's 2 KB).
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*/
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#define MOSTEK_48T08_OFFSET 0x0000UL /* Lower NVRAM portions */
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#define MOSTEK_48T08_48T02 0x1800UL /* Offset to 48T02 chip */
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/* SUN5 systems usually have 48t59 model clock chipsets. But we keep the older
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* clock chip definitions around just in case.
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*/
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#define MOSTEK_48T59_OFFSET 0x0000UL /* Lower NVRAM portions */
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#define MOSTEK_48T59_48T02 0x1800UL /* Offset to 48T02 chip */
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#endif /* !(_SPARC64_MOSTEK_H) */
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